Datasheet > CY7C09349A

CY7C09349A

更新时间： 2024-11-09 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
17页	338K
描述
4K/8K x 18 Synchronous Dual-Port Static RAM

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中文翻译

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数据手册

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CY7C09349A 数据手册

25/0251

CY7C09349A

CY7C09359A

4K/8K x 18

Synchronous Dual-Port Static RAM

• Low operating power

Features

—Active = 200 mA (typical)

• True dual-ported memory cells which allow simulta-

neous access of the same memory location

—Standby = 0.05 mA (typical)

• Fully synchronous interface for easier operation

• Burst counters increment addresses internally

—Shorten cycle times

• Two Flow-Through/Pipelined devices

— 4K x 18 organization (CY7C09349A)

— 8K x 18 organization (CY7C09359A)

• Three Modes

—Minimize bus noise

—Supported in Flow-Through and Pipelined modes

• Dual Chip Enables for easy depth expansion

• Upper and lower byte controls for bus matching

• Automatic power-down

• Commercial and Industrial temperature ranges

• Available in 100-pin TQFP

— Flow-Through

— Pipelined

— Burst

• Pipelined output mode on both ports allows fast

100-MHz cycle time

• 0.35-micron CMOS for optimum speed/power

• High-speed clock to data access 6.5^[1]/7.5/9/12 ns

(max.)

Logic Block Diagram

R/W_L

UB_L

R/W_R

UB_R

CE_0L

CE_0R

CE_1L

LB_L

CE_1R

LB_R

0/1

OE_L

OE_R

1b 0b 1a 0a

0a 1a 0b 1b

0/1

FT/Pipe_L

FT/Pipe_R

I/O_9L–I/O_17L

I/O_9R–I/O_17R

I/O

Control

I/O

Control

I/O_0L–I/O_8L

I/O_0R–I/O_8R

12/13

[2]

A_0L–A

A_0R–A_11/12R

11/12L

Counter/

Address

Decode

Counter/

Address

Decode

CLK_L

ADS_L

CLK_R

ADS_R

True Dual-Ported

RAM Array

CNTEN_L

CNTEN_R

CNTRST_R

CNTRST_L

Notes:

1. See page 6 for Load Conditions.

2. A₀–A₁₁for 4K; A₀–A₁₂for 8K devices.

For the most recent information, visit the Cypress web site at www.cypress.com

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-06048 Rev. **

Revised September 19, 2001

12 3 4 5 6 7...17

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CY7C09349AV-12ACT	CYPRESS	获取价格	暂无描述
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