Datasheet > 存储 > SRAM> CY7C056V-12BBC

CY7C056V-12BBC

更新时间： 2024-09-17 22:17:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
23页	461K
描述
3.3V 16K/32K x 36 FLEx36 Asynchronous Dual-Port Static RAM

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CY7C056V-12BBC 数据手册

25/0251

CY7C056V

CY7C057V

3.3V 16K/32K x 36

FLEx36™ Asynchronous Dual-Port Static RAM

• Expandable data bus to 72 bits or more using Mas-

ter/Slave Chip Select when using more than one device

Features

• True dual-ported memory cells which allow simulta-

neous access of the same memory location

• On-Chip arbitration logic

• Semaphores included to permit software handshaking

between ports

• 16K x 36 organization (CY7C056V)

• 32K x 36 organization (CY7C057V)

• 0.25-micron CMOS for optimum speed/power

• High-speed access: 12/15/20 ns

• Low operating power

• INT flag for port-to-port communication

• Byte Select on Left Port

• Bus Matching on Right Port

• Depth Expansion via dual chip enables

• Pin select for Master or Slave

• Commercial and Industrial Temperature Ranges

• Compact package

— Active: I_CC= 250 mA (typical)

— Standby: I_SB3= 10 µA (typical)

• Fully asynchronous operation

• Automatic power-down

—144-Pin TQFP (20 x 20 x 1.4 mm)

—172-Ball BGA (1.0-mm pitch) (15 x 15 x.51 mm)

Logic Block Diagram

R/W_L

R/W_R

B₀–B₃

CE_0L

CE_1L

Left

Port

Control

Logic

Right

CE_0R

CE_1R

Port

Control

Logic

CE_L

CE_R

OE_L

OE_R

I/O_0L–I/O_8L

9/18/36

I/O_9L–I/O_17L

I/O_18L–I/O_26L

I/O_27L–I/O_35L

Bus

Match

I/O_R

I/O

Control

I/O

Control

SIZE

14/15

[1]

Address

Decode

Address

Decode

True Dual-Ported

A_0L–A_13/14L

A_0R–A_13/14R

RAM Array

14/15

Interrupt

Semaphore

Arbitration

SEM_L

SEM_R

[2]

BUSY_L^[2]

INT_L

BUSY_R

INT_R

M/S

Notes:

1. A₀–A₁₃for 16K; A₀–A₁₄for 32K devices.

2. BUSY is an output in Master mode and an input in Slave mode.

For the most recent information, visit the Cypress web site at www.cypress.com

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-06055 Rev. **

Revised September 7, 2001

12 3 4 5 6 7...23

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