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CY7C0450V18-167BBC PDF预览

CY7C0450V18-167BBC

更新时间: 2024-09-18 17:28:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
51页 962K
描述
Multi-Port SRAM, 32KX40, 3.5ns, CMOS, PBGA676

CY7C0450V18-167BBC 技术参数

生命周期:Active包装说明:BGA, BGA676,26X26,40
Reach Compliance Code:compliant风险等级:5.8
最长访问时间:3.5 ns最大时钟频率 (fCLK):167 MHz
I/O 类型:COMMONJESD-30 代码:S-PBGA-B676
内存密度:1310720 bit内存集成电路类型:MULTI-PORT SRAM
内存宽度:40端口数量:4
端子数量:676字数:32768 words
字数代码:32000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX40输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA676,26X26,40封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
电源:1.8 V认证状态:Not Qualified
最大待机电流:0.00001 A最小待机电流:1.71 V
子类别:SRAMs最大压摆率:1.3 mA
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOMBase Number Matches:1

CY7C0450V18-167BBC 数据手册

 浏览型号CY7C0450V18-167BBC的Datasheet PDF文件第2页浏览型号CY7C0450V18-167BBC的Datasheet PDF文件第3页浏览型号CY7C0450V18-167BBC的Datasheet PDF文件第4页浏览型号CY7C0450V18-167BBC的Datasheet PDF文件第5页浏览型号CY7C0450V18-167BBC的Datasheet PDF文件第6页浏览型号CY7C0450V18-167BBC的Datasheet PDF文件第7页 
CY7C0452V18/0451V18/0450V18  
CY7C0431V18/0430V18  
PRELIMINARY  
QuadPort™ Datapath Switching Element (DSE) Family  
• Simple array partitioning (except CY7C0452V18)  
— Internal mask register for burst counter control  
Features  
• The QuadPort™ Datapath Switching Element (DSE)  
allows four independent ports of access for data path  
management and switching.  
— Counter-Interrupt flags to indicate terminal count  
— Block Retransmit Capability  
• Synchronous pipelined device  
— 128K x 40 (5 Mb) CY7C0452V18  
— 64K x 40 (2 Mb) CY7C0451V18  
— 32K x 40 (1 Mb) CY7C0450V18  
— 128K x 20 (2 Mb) CY7C0431V18  
— Counter and mask register readback on address  
lines  
• DualChipEnablesonallportsforeasydepthexpansion  
(except CY7C0452V18)  
• Separate byte select controls on all ports  
• BGA package (676 balls, 27 x 27 mm, 1.0 mm pitch)  
• Commercial and Industrial temperature ranges  
• IEEE 1149.1 JTAG boundary scan  
— 64K x 20 (1 Mb) CY7C0430V18  
• Clock operation up to 167 MHz  
• High Bandwidth up to 27 Gbps  
• LVTTL and SSTL2 I/O standard for I/O  
• LVPECL differential clock inputs  
• Impedance matching on data outputs  
• 1.8V Supply Voltage  
— Active = 1300 mA (maximum)  
— Standby = 500 mA (maximum)  
QuadPort DSE Applications  
PORT 1  
PORT 3  
PORT 2  
PORT 4  
BUFFERED SWITCH  
PORT 2  
PORT 3  
PORT 4  
PORT 1  
REDUNDANT DATA MIRROR  
PORT 1  
PORT 2  
PORT 3  
PORT 4  
DATA PATH AGGREGATOR  
Cypress Semiconductor Corporation  
Document #: 38-06065 Rev. **  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised August 2, 2002  

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