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CY7C024-55JI PDF预览

CY7C024-55JI

更新时间： 2024-11-07 00:01:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
20页 771K
描述
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY

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CY7C024-55JI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：LCC包装说明：PLASTIC, LCC-84
针数：84Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：5.48最长访问时间：55 ns
其他特性：INTERRUPT FLAGI/O 类型：COMMON
JESD-30 代码：S-PQCC-J84JESD-609代码：e0
长度：29.3116 mm内存密度：65536 bit
内存集成电路类型：DUAL-PORT SRAM内存宽度：16
功能数量：1端口数量：2
端子数量：84字数：4096 words
字数代码：4000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：4KX16输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC84,1.2SQ
封装形状：SQUARE封装形式：CHIP CARRIER
并行/串行：PARALLEL电源：5 V
认证状态：Not Qualified座面最大高度：5.08 mm
最大待机电流：0.015 A最小待机电流：2 V
子类别：SRAMs最大压摆率：0.25 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
宽度：29.3116 mmBase Number Matches：1

CY7C024-55JI 数据手册

 浏览型号CY7C024-55JI的Datasheet PDF文件第2页浏览型号CY7C024-55JI的Datasheet PDF文件第3页浏览型号CY7C024-55JI的Datasheet PDF文件第4页浏览型号CY7C024-55JI的Datasheet PDF文件第5页浏览型号CY7C024-55JI的Datasheet PDF文件第6页浏览型号CY7C024-55JI的Datasheet PDF文件第7页 
CY7C024/0241  
CY7C025/0251  
4K x 16/18 and 8K x 16/18 Dual-Port  
Static RAM with SEM, INT, BUSY  
Features  
Functional Description  
• True Dual-Ported memory cells which allow  
The CY7C024/0241 and CY7C025/0251 are low-power  
simultaneous reads of the same memory location  
• 4K x 16 organization (CY7C024)  
• 4K x 18 organization (CY7C0241)  
• 8K x 16 organization (CY7C025)  
• 8K x 18 organization (CY7C0251)  
• 0.65-micron CMOS for optimum speed/power  
• High-speed access: 15 ns  
CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs. Var-  
ious arbitration schemes are included on the CY7C024/0241  
and CY7C025/0251 to handle situations when multiple pro-  
cessors access the same piece of data. Two ports are provid-  
ed, permitting independent, asynchronous access for reads  
and writes to any location in memory. The CY7C024/0241 and  
CY7C025/0251 can be utilized as standalone 16-/18-bit du-  
al-port static RAMs or multiple devices can be combined in  
order to function as a 32-/36-bit or wider master/slave du-  
al-port static RAM. An M/S pin is provided for implementing  
32-/36-bit or wider memory applications without the need for  
separate master and slave devices or additional discrete logic.  
Application areas include interprocessor/multiprocessor de-  
signs, communications status buffering, and dual-port vid-  
eo/graphics memory.  
• Low operating power: ICC = 150 mA (typ.)  
• Fully asynchronous operation  
• Automatic power-down  
• Expandable data bus to 32/36 bits or more using  
Master/Slave chip select when using more than one  
device  
• On-chip arbitration logic  
• Semaphores included to permit software handshaking  
between ports  
Each port has independent control pins: Chip Enable (CE),  
Read or Write Enable (R/W), and Output Enable (OE). Two flags  
are provided on each port (BUSY and INT). BUSY signals that the  
port is trying to access the same location currently being accessed by  
the other port. The Interrupt Flag (INT) permits communication be-  
tween ports or systems by means of a mail box. The semaphores are  
used to pass a flag, or token, from one port to the other to indicate that  
a shared resource is in use. The semaphore logic is comprised of  
eight shared latches. Only one sidecan control the latch (semaphore)  
at any time. Control of a semaphore indicates that a shared resource  
is in use. An automatic power-down feature is controlled indepen-  
dently on each port by a chip select (CE) pin.  
• INT flag for port-to-port communication  
• Separate upper-byte and lower-byte control  
• Pin select for Master or Slave  
• Available in 84-pin PLCC and 100-pin TQFP  
The CY7C024/0241 and CY7C025/0251 are available in  
84-pin PLCCs (CY7C024 and CY7C025 only) and 100-pin  
Thin Quad Plastic Flatpack (TQFP).  
v
Logic Block Diagram  
R/W  
L
R/W  
R
UB  
L
UB  
R
LB  
R
LB  
L
OE  
L
L
CE  
CE  
OE  
R
R
[3]  
15L  
[3]  
[2]  
–
–
I/O –I/O  
8L  
I/O  
I/O  
I/O  
8R  
0R  
15R  
I/O  
CONTROL  
I/O  
CONTROL  
[2]  
I/O –I/O  
0L  
I/O  
[1]  
7L  
7R  
[1]  
BUSY  
BUSY  
R
L
(CY7C025/0251)  
A
12R  
(CY7C025/0251)  
A
12L  
MEMORY  
ARRAY  
A
11L  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
A
11R  
A
0L  
A
0R  
INTERRUPT  
SEMAPHORE  
ARBITRATION  
CE  
OE  
CE  
L
L
R
OE  
UB  
LB  
R
R
UB  
LB  
L
L
R
R/W  
R/W  
R
L
SEM  
SEM  
7C024–1  
R
L
INT  
L
M/S  
INT  
R
Cypress Semiconductor Corporation  
Document #: 38-06035 Rev. *B  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised June 22, 2004  
1234567...20

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