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CY7C024AV-25AI PDF预览

CY7C024AV-25AI

更新时间: 2024-11-08 22:41:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
19页 242K
描述
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM

CY7C024AV-25AI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, TQFP-100
针数:100Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.75最长访问时间:25 ns
I/O 类型:COMMONJESD-30 代码:S-PQFP-G100
JESD-609代码:e0长度:14 mm
内存密度:65536 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:16湿度敏感等级:3
功能数量:1端口数量:2
端子数量:100字数:4096 words
字数代码:4000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:4KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.00005 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.185 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

CY7C024AV-25AI 数据手册

 浏览型号CY7C024AV-25AI的Datasheet PDF文件第2页浏览型号CY7C024AV-25AI的Datasheet PDF文件第3页浏览型号CY7C024AV-25AI的Datasheet PDF文件第4页浏览型号CY7C024AV-25AI的Datasheet PDF文件第5页浏览型号CY7C024AV-25AI的Datasheet PDF文件第6页浏览型号CY7C024AV-25AI的Datasheet PDF文件第7页 
CY7C024AV/025AV/026AV  
CY7C0241AV/0251AV/036AV  
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM  
• Fully asynchronous operation  
• Automatic power-down  
• Expandable data bus to 32/36 bits or more using  
Master/Slave chip select when using more than one  
device  
• On-chip arbitration logic  
• Semaphores included to permit software handshaking  
between ports  
• INT flag for port-to-port communication  
• Separate upper-byte and lower-byte control  
• Pin select for Master or Slave  
• Commercial and industrial temperature ranges  
• Available in 100-pin TQFP  
Features  
• True dual-ported memory cells which allow  
simultaneous access of the same memory location  
• 4/8/16K × 16 organization (CY7C024AV/025AV/026AV)  
• 4/8K × 18 organization (CY7C0241AV/0251AV)  
• 16K × 18 organization (CY7C036AV)  
• 0.35-micron CMOS for optimum speed/power  
• High-speed access: 20 and 25 ns  
• Low operating power  
— Active: ICC = 115 mA (typical)  
Standby: ISB3 = 10 µA (typical)  
Logic Block Diagram  
R/W  
R/W  
UB  
L
R
R
UB  
L
CE  
CE  
LB  
L
R
LB  
L
R
OE  
OE  
R
L
[1]  
8/9  
8/9  
8/9  
8/9  
[1]  
15/17L  
I/O  
–I/O  
I/O  
–I/O  
8/9L  
8/9L  
15/17R  
[2]  
I/O  
Control  
I/O  
Control  
[2]  
7/8L  
I/O –I/O  
I/O –I/O  
7/8R  
0L  
0L  
12/13/14  
12/13/14  
[3]  
[3]  
Address  
Decode  
Address  
Decode  
True Dual-Ported  
A –A  
A
A
–A  
0L 11/1213L  
0R 11/12/13R  
RAM Array  
[3]  
[3]  
12/13/14  
12/13/14  
A –A  
–A  
0L 11/12/13L  
0R 11/12/13R  
CE  
CE  
Interrupt  
Semaphore  
Arbitration  
L
R
OE  
OE  
L
R
R/W  
R/W  
L
R
SEM  
SEM  
L
R
[4]  
[4]  
BUSY  
BUSY  
INT  
UB  
L
R
R
R
R
INT  
L
UB  
L
LB  
M/S  
LB  
L
Notes:  
1. I/O –I/O for x16 devices; I/O –I/O for x18 devices.  
8
15  
9
17  
2. I/O –I/O for x16 devices; I/O –I/O for x18 devices.  
0
7
0
8
3. A –A for 4K devices; A –A for 8K devices; A –A for 16K devices.  
0
11  
0
12  
0
13  
4. BUSY is an output in master mode and an input in slave mode.  
Cypress Semiconductor Corporation  
Document #: 38-06052 Rev. *E  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised October 12, 2004  

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