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CY7C024AV_05 PDF预览

CY7C024AV_05

更新时间: 2024-09-18 04:53:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
19页 248K
描述
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM

CY7C024AV_05 数据手册

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CY7C024AV/025AV/026AV  
CY7C0241AV/0251AV/036AV  
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM  
• Automatic power-down  
Features  
• Expandable data bus to 32/36 bits or more using  
Master/Slave chip select when using more than one  
device  
• True dual-ported memory cells which allow  
simultaneous access of the same memory location  
• 4/8/16K × 16 organization (CY7C024AV/025AV/026AV)  
• 4/8K × 18 organization (CY7C0241AV/0251AV)  
• 16K × 18 organization (CY7C036AV)  
• 0.35-micron CMOS for optimum speed/power  
• High-speed access: 20 and 25 ns  
• On-chip arbitration logic  
• Semaphores included to permit software handshaking  
between ports  
• INT flag for port-to-port communication  
• Separate upper-byte and lower-byte control  
• Pin select for Master or Slave  
• Low operating power  
• Commercial and industrial temperature ranges  
• Available in 100-pin Lead (Pb)-free TQFP and 100-pin  
TQFP  
— Active: ICC = 115 mA (typical)  
Standby: ISB3 = 10 μA (typical)  
• Fully asynchronous operation  
Logic Block Diagram  
R/WL  
UBL  
R/WR  
UBR  
CEL  
CER  
LBL  
LBR  
OEL  
OER  
[1]  
8/9  
[1]  
8/9  
I/O8/9L–I/O15/17L  
I/O8/9L–I/O15/17R  
[2]  
8/9  
8/9  
I/O  
Control  
I/O  
Control  
[2]  
I/O0L–I/O7/8L  
I/O0L–I/O7/8R  
12/13/14  
12/13/14  
[3]  
[3]  
Address  
Decode  
Address  
Decode  
True Dual-Ported  
A0L–A11/1213L  
A0R–A11/12/13R  
RAM Array  
[3]  
[3]  
12/13/14  
12/13/14  
A0L–A11/12/13L  
A0R–A11/12/13R  
CER  
CEL  
Interrupt  
Semaphore  
Arbitration  
OEL  
R/WL  
OER  
R/WR  
SEML  
[4]  
SEMR  
[4]  
BUSYL  
INTL  
UBL  
BUSYR  
INTR  
UBR  
LBL  
M/S  
LBR  
Notes:  
1. I/O –I/O for x16 devices; I/O –I/O for x18 devices.  
8
15  
9
17  
2. I/O –I/O for x16 devices; I/O –I/O for x18 devices.  
0
7
0
8
3. A –A for 4K devices; A –A for 8K devices; A –A for 16K devices.  
0
11  
0
12  
0
13  
4. BUSY is an output in master mode and an input in slave mode.  
Cypress Semiconductor Corporation  
Document #: 38-06052 Rev. *H  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised June 15, 2005  

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