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CY7C024AV_09 PDF预览

CY7C024AV_09

更新时间: 2024-09-18 06:51:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
19页 458K
描述
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM

CY7C024AV_09 数据手册

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CY7C024AV/024BV/025AV/026AV  
CY7C0241AV/0251AV/036AV  
3.3V 4K/8K/16K x 16/18 Dual-Port  
Static RAM  
Fully asynchronous operation  
Automatic power down  
Features  
True dual-ported memory cells which enable simultaneous  
access of the same memory location  
Expandable data bus to 32 bits, 36 bits or more using Master  
and Slave chip select when using more than one device  
4, 8 or 16K × 16 organization  
On chip arbitration logic  
(CY7C024AV/024BV [1]/ 025AV/026AV)  
4 or 8K × 18 organization (CY7C0241AV/0251AV)  
16K × 18 organization (CY7C036AV)  
0.35 micron CMOS for optimum speed and power  
High speed access: 20 and 25 ns  
Semaphores included to permit software handshaking  
between ports  
INT flag for port-to-port communication  
Separate upper byte and lower byte control  
Pin select for Master or Slave (M/S)  
Low operating power  
Commercial and industrial temperature ranges  
Available in 100-pin Pb-free TQFP and 100-pin TQFP  
Active: ICC = 115 mA (typical)  
Standby: ISB3 = 10 μA (typical)  
Logic Block Diagram  
R/WL  
UBL  
R/WR  
UBR  
CEL  
CER  
LBL  
LBR  
OEL  
OER  
[2]  
8/9  
8/9  
8/9  
[2]  
IO8/9L–IO15/17L  
IO8/9L–IO15/17R  
[3]  
8/9  
IO  
Control  
IO  
Control  
[3]  
IO0L–IO7/8L  
IO0L–IO7/8R  
12/13/14  
12/13/14  
[4]  
A0R–A11/12/13R  
Address  
Decode  
Address  
Decode  
[4]  
True Dual-Ported  
RAM Array  
A0L–A11/1213L  
[4]  
[4]  
12/13/14  
12/13/14  
A0L–A11/12/13L  
A0R–A11/12/13R  
CER  
CEL  
Interrupt  
Semaphore  
Arbitration  
OEL  
R/WL  
OER  
R/WR  
SEML  
SEMR  
[5]  
[5]  
BUSYL  
INTL  
UBL  
BUSYR  
INTR  
UBR  
LBL  
M/S  
LBR  
Notes  
1. CY7C024AV and CY7C024BV are functionally identical.  
2. IO –IO for x16 devices; IO –IO for x18 devices.  
8
15  
9
17  
3. IO –IO for x16 devices; IO –IO for x18 devices.  
0
7
0
8
4. A –A for 4K devices; A –A for 8K devices; A –A for 16K devices.  
0
11  
0
12  
0
13  
5. BUSY is an output in master mode and an input in slave mode.  
Cypress Semiconductor Corporation  
Document #: 38-06052 Rev. *J  
198 Champion Court  
San Jose  
,
CA 95134-1709  
408-943-2600  
Revised December 10, 2008  
[+] Feedback  

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