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CY62146VLL-70ZI

更新时间： 2024-11-22 22:34:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 229K
描述
4M (256K x 16) Static RAM

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中文翻译

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CY62146VLL-70ZI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：TSOP2
包装说明：TSOP2-44针数：44
Reach Compliance Code：not_compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.71
最长访问时间：70 ns其他特性：TTL-COMPATIBLE INPUTS & OUTPUTS
I/O 类型：COMMONJESD-30 代码：R-PDSO-G44
JESD-609代码：e0长度：18.41 mm
内存密度：4194304 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：44
字数：262144 words字数代码：256000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSOP2封装等效代码：TSOP44,.46,32
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
电源：3 V认证状态：Not Qualified
座面最大高度：1.2 mm最大待机电流：0.0000055 A
最小待机电流：1 V子类别：SRAMs
最大压摆率：0.015 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：10.16 mmBase Number Matches：1

CY62146VLL-70ZI 数据手册

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®
CY62146V MoBL  
4M (256K x 16) Static RAM  
deselected (CE HIGH). The input/output pins (I/O0 through  
I/O15) are placed in a high-impedance state when: deselected  
(CE HIGH), outputs are disabled (OE HIGH), BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
Features  
• Wide voltage range: 2.7V–3.6V  
• Ultra-low active, standby power  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A16). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A17).  
• Package available in a standard 44-Pin TSOP Type II  
(forward pinout) package  
Functional Description[1]  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
The CY62146V is a high-performance CMOS static RAM  
organized as 256K words by 16 bits. These devices feature  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life® (MoBL®) in  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that significantly  
reduces power consumption by 99% when addresses are not  
toggling. The device can also be put into standby mode when  
Logic Block Diagram  
DATA IN DRIVERS  
A
10  
A
A
A
9
8
7
6
A
A
A
A
256K × 16  
5
4
RAM Array  
I/O – I/O  
0
7
2048 × 2048  
3
2
I/O – I/O  
A
A
A
8
15  
1
0
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05159 Rev. *A  
Revised August 27, 2002  
1234567...10

中文翻译

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