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CY62147CV18LL-55BAI PDF预览

CY62147CV18LL-55BAI

更新时间： 2024-11-22 22:22:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 275K
描述
256K x 16 Static RAM

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中文翻译

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CY62147CV18LL-55BAI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：7 X 8.50 MM, 1.20 MM HEIGHT, FBGA-48
针数：48Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.68最长访问时间：55 ns
I/O 类型：COMMONJESD-30 代码：R-PBGA-B48
JESD-609代码：e0长度：8.5 mm
内存密度：4194304 bit内存集成电路类型：STANDARD SRAM
内存宽度：16功能数量：1
端子数量：48字数：262144 words
字数代码：256000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装等效代码：BGA48,6X8,30封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行：PARALLEL
电源：1.8 V认证状态：Not Qualified
座面最大高度：1.2 mm最大待机电流：0.000008 A
最小待机电流：1 V子类别：SRAMs
最大压摆率：0.007 mA最大供电电压 (Vsup)：1.95 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：0.75 mm
端子位置：BOTTOM宽度：7 mm
Base Number Matches：1

CY62147CV18LL-55BAI 数据手册

 浏览型号CY62147CV18LL-55BAI的Datasheet PDF文件第2页浏览型号CY62147CV18LL-55BAI的Datasheet PDF文件第3页浏览型号CY62147CV18LL-55BAI的Datasheet PDF文件第4页浏览型号CY62147CV18LL-55BAI的Datasheet PDF文件第5页浏览型号CY62147CV18LL-55BAI的Datasheet PDF文件第6页浏览型号CY62147CV18LL-55BAI的Datasheet PDF文件第7页 
CY62147CV18 MoBL2™  
256K x 16 Static RAM  
power consumption by 99% when addresses are not toggling.  
The device can also be put into standby mode when deselect-  
ed (CE HIGH or both BLE and BHE are HIGH). The input/out-  
put pins (I/O0 through I/O15) are placed in a high-impedance  
state when: deselected (CE HIGH), outputs are disabled (OE  
HIGH), both Byte High Enable and Byte Low Enable are dis-  
abled (BHE, BLE HIGH), or during a write operation (CE LOW  
and WE LOW).  
Features  
• High Speed  
— 55 ns and 70 ns availability  
• Low voltage range:  
— CY62147CV18: 1.65V−1.95V  
• Pin Compatible w/ CY62147V18/BV18  
• Ultra-low active power  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A17). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A17).  
— Typical Active Current: 0.5 mA @ f = 1 MHz  
— Typical Active Current: 2 mA @ f = fmax (70 ns speed)  
• Low standby power  
• Easy memory expansion with CE and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Reading from the device is accomplished by taking Chip En-  
able (CE) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then  
data from the memory location specified by the address pins  
will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW,  
then data from memory will appear on I/O8 to I/O15. See the  
Truth Table at the back of this data sheet for a complete de-  
scription of read and write modes.  
Functional Description  
The CY62147CV18 is a high-performance CMOS static RAM  
organized as 256K words by 16 bits. This device features ad-  
vanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life™ (MoBL™) in portable  
applications such as cellular telephones. The device also has  
an automatic power-down feature that significantly reduces  
The CY62147CV18 is available in a 48-ball FBGA package.  
Logic Block Diagram  
DATA IN DRIVERS  
A
10  
9
A
A
8
A
7
A
A
256K x 16  
6
RAM Array  
I/O –I/O  
5
0
7
A
2048 X 2048  
4
I/O –I/O  
A
8
15  
3
A
A
2
1
A
0
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
CE  
Power -Down  
Circuit  
BHE  
BLE  
MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation.  
Cypress Semiconductor Corporation  
Document #: 38-05011 Rev. *B  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised October 31, 2001  
1234567...12

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