Datasheet > CY62147CV25

CY62147CV25

更新时间： 2024-11-18 22:22:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
14页	303K
描述
256K x 16 Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY62147CV25 数据手册

47V

CY62147CV25/30/33

MoBL™

256K x 16 Static RAM

cantly reduces power consumption by 80% when addresses

are not toggling. The device can also be put into standby mode

reducing power consumption by more than 99% when dese-

lected (CE HIGH or both BLE and BHE are HIGH). The in-

put/output pins (I/O₀through I/O₁₅) are placed in a high-im-

pedance state when: deselected (CE HIGH), outputs are

disabled (OE HIGH), both Byte High Enable and Byte Low

Enable are disabled (BHE, BLE HIGH), or during a write oper-

ation (CE LOW and WE LOW).

Features

• High Speed

— 55 ns and 70 ns availability

• Voltage range:

— CY62147CV25: 2.2V–2.7V

— CY62147CV30: 2.7V–3.3V

— CY62147CV33: 3.0V–3.6V

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇), is

written into the location specified on the address pins (A₀

through A₁₇). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O₈through I/O₁₅) is written into the location

specified on the address pins (A₀through A₁₇).

• Pin Compatible with CY62147V

• Ultra-low active power

— Typical active current: 1.5 mA @ f = 1 MHz

— Typicalactivecurrent:5.5mA@f=f_max(70nsspeed)

• Low standby power

• Easy memory expansion with CE and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O₀to I/O₇. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O₈to I/O₁₅. See

the truth table at the back of this data sheet for a complete

description of read and write modes.

Functional Description

The CY62147CV25/30/33 are high-performance CMOS static

RAMs organized as 256K words by 16 bits. These devices

feature advanced circuit design to provide ultra-low active cur-

rent. This is ideal for providing More Battery Life™ (MoBL™)

in portable applications such as cellular telephones. The de-

vices also have an automatic power-down feature that signifi-

The CY62147CV25/30/33 are available in a 48-ball FBGA

package.

Logic Block Diagram

DATA IN DRIVERS

256K x 16

RAM Array

I/O – I/O

2048 x 2048

I/O – I/O

COLUMN DECODER

BHE

BLE

Power -Down

Circuit

BHE

BLE

Cypress Semiconductor Corporation

Document #: 38-05202 Rev. *A

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised April 24, 2002

12 3 4 5 6 7...14

中文翻译

下载PDF

与CY62147CV25相关器件

型号	品牌	获取价格	描述	数据表
CY62147CV25LL-55BAI	CYPRESS	获取价格	256K x 16 Static RAM
CY62147CV25LL-55BVI	CYPRESS	获取价格	256K x 16 Static RAM
CY62147CV25LL-70BAI	CYPRESS	获取价格	256K x 16 Static RAM
CY62147CV25LL-70BAIT	CYPRESS	获取价格	暂无描述
CY62147CV25LL-70BVI	CYPRESS	获取价格	256K x 16 Static RAM
CY62147CV25LL-70BVIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48
CY62147CV30	CYPRESS	获取价格	256K x 16 Static RAM
CY62147CV30LL-55BAI	CYPRESS	获取价格	256K x 16 Static RAM
CY62147CV30LL-55BAIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, FBGA-48
CY62147CV30LL-55BVI	CYPRESS	获取价格	256K x 16 Static RAM

与CY62147CV25相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

23
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

15
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

45
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

45

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62147CV25

CY62147CV25 数据手册

与CY62147CV25相关器件

与CY62147CV25相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62147CV25

CY62147CV25 数据手册

与CY62147CV25相关器件

与CY62147CV25相关文章

您还可以找

您在本页遇到什么问题？