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CY62147CV30LL-70BAIT

更新时间： 2024-11-23 19:21:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
14页 303K
描述
Standard SRAM, 256KX16, 70ns, CMOS, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, FINE PITCH, TBGA-48

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CY62147CV30LL-70BAIT 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：7 X 8.50 MM, 1.20 MM HEIGHT, FINE PITCH, TBGA-48针数：48
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41Factory Lead Time：1 week
风险等级：5.62最长访问时间：70 ns
JESD-30 代码：R-PBGA-B48JESD-609代码：e0
长度：8.5 mm内存密度：4194304 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
功能数量：1端子数量：48
字数：262144 words字数代码：256000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX16
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.3 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：BALL端子节距：0.75 mm
端子位置：BOTTOM宽度：7 mm
Base Number Matches：1

CY62147CV30LL-70BAIT 数据手册

 浏览型号CY62147CV30LL-70BAIT的Datasheet PDF文件第2页浏览型号CY62147CV30LL-70BAIT的Datasheet PDF文件第3页浏览型号CY62147CV30LL-70BAIT的Datasheet PDF文件第4页浏览型号CY62147CV30LL-70BAIT的Datasheet PDF文件第5页浏览型号CY62147CV30LL-70BAIT的Datasheet PDF文件第6页浏览型号CY62147CV30LL-70BAIT的Datasheet PDF文件第7页 
47V  
CY62147CV25/30/33  
MoBL™  
256K x 16 Static RAM  
cantly reduces power consumption by 80% when addresses  
are not toggling. The device can also be put into standby mode  
reducing power consumption by more than 99% when dese-  
lected (CE HIGH or both BLE and BHE are HIGH). The in-  
put/output pins (I/O0 through I/O15) are placed in a high-im-  
pedance state when: deselected (CE HIGH), outputs are  
disabled (OE HIGH), both Byte High Enable and Byte Low  
Enable are disabled (BHE, BLE HIGH), or during a write oper-  
ation (CE LOW and WE LOW).  
Features  
• High Speed  
— 55 ns and 70 ns availability  
• Voltage range:  
— CY62147CV25: 2.2V–2.7V  
— CY62147CV30: 2.7V–3.3V  
— CY62147CV33: 3.0V–3.6V  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A17). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A17).  
• Pin Compatible with CY62147V  
• Ultra-low active power  
— Typical active current: 1.5 mA @ f = 1 MHz  
— Typicalactivecurrent:5.5mA@f=fmax (70nsspeed)  
• Low standby power  
• Easy memory expansion with CE and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
Functional Description  
The CY62147CV25/30/33 are high-performance CMOS static  
RAMs organized as 256K words by 16 bits. These devices  
feature advanced circuit design to provide ultra-low active cur-  
rent. This is ideal for providing More Battery Life™ (MoBL™)  
in portable applications such as cellular telephones. The de-  
vices also have an automatic power-down feature that signifi-  
The CY62147CV25/30/33 are available in a 48-ball FBGA  
package.  
Logic Block Diagram  
DATA IN DRIVERS  
A
10  
9
A
A
8
7
6
A
A
A
A
A
256K x 16  
5
4
RAM Array  
I/O – I/O  
0
7
2048 x 2048  
3
I/O – I/O  
A
8
15  
2
A
A
1
0
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
CE  
Power -Down  
Circuit  
BHE  
BLE  
Cypress Semiconductor Corporation  
Document #: 38-05202 Rev. *A  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised April 24, 2002  
1234567...14

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