Datasheet > CY621472GN30

CY621472GN30

更新时间： 2024-11-20 01:05:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
20页	298K
描述
4-Mbit (256K words Ã 16 bit) Static RAM

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CY621472GN30 数据手册

CY62147GN/CY621472GN MoBL^®

4-Mbit (256K words × 16 bit) Static RAM

4-Mbit (256K words

× 16 bit) Static RAM

Features

Functional Description

■ High speed: 45 ns/55 ns

CY62147GN and CY621472GN are high-performance CMOS

low-power (MoBL) SRAM devices organized as 256K Words by

16-bits. Both devices are offered in single and dual chip enable

options and in multiple pin configurations.

■ Ultra-low standby power

❐ Typical standby current: 3.5 A

❐ Maximum standby current: 8.7 A

Devices with a single chip enable input are accessed by

■ Widevoltage range: 1.65 V to2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V

■ 1.0-V data retention

asserting the chip enable (CE) input LOW. Dual chip enable

devices are accessed by asserting both chip enable inputs – CE₁

as low and CE₂as HIGH.

■ TTL-compatible inputs and outputs

Data writes are performed by asserting the Write Enable (WE)

input LOW, while providing the data on I/O₀through I/O₁₅and

address on A₀through A₁₇pins. The Byte High Enable (BHE)

and Byte Low Enable (BLE) inputs control write operations to the

upper and lower bytes of the specified memory location. BHE

controls I/O₈through I/O₁₅and BLE controls I/O₀through I/O₇.

■ Pb-free 48-ball VFBGA and 44-pin TSOP II packages

Data reads are performed by asserting the Output Enable (OE)

input and providing the required address on the address lines.

Read data is accessible on the I/O lines (I/O₀through I/O₁₅).

Byte accesses can be performed by asserting the required byte

enable signal (BHE or BLE) to read either the upper byte or the

lower byte of data from the specified address location.

All I/Os (I/O₀through I/O₁₅) are placed in a HI-Z state when the

device is deselected (CE HIGH for a single chip enable device

and CE₁HIGH/CE₂LOW for a dual chip enable device), or

control signals are de-asserted (OE, BLE, BHE).

The device also has a unique Byte Power down feature, where,

if both the Byte Enables (BHE and BLE) are disabled, the

devices seamlessly switch to standby mode irrespective of the

state of the chip enables, thereby saving power.

The logic block diagram is provided in page 2.

Product Portfolio

Power Dissipation

Features and

Options

(see the Pin

Configurations

section)

Operating I_CC, (mA)

Standby, I_SB2(µA)

Product

Range

V_CCRange (V) Speed (ns)

f = f_max

Typ^[1]

Max

Typ^[1]

Max

CY62147GN18

Industrial

1.65 V–2.2 V

2.2 V–3.6 V

3.5

Single or dual

Chip Enables

CY62147GN30

CY621472GN30

8.7

CY62147GN

4.5 V–5.5 V

Notes

1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V–2.2 V),

= 3 V (for V range of 2.2 V–3.6 V), and V = 5 V (for V range of 4.5 V–5.5 V), T = 25 °C.

Cypress Semiconductor Corporation

Document Number: 002-10624 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 21, 2017

12 3 4 5 6 7...20

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与CY621472GN30相关器件

型号	品牌	获取价格	描述	数据表
CY621472GN30-45ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY621472GN30-45ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY62147BV18LL-70BAI	ETC	获取价格	x16 SRAM
CY62147CV18	CYPRESS	获取价格	256K x 16 Static RAM
CY62147CV18_02	CYPRESS	获取价格	256K x 16 Static RAM
CY62147CV18LL-55BAI	CYPRESS	获取价格	256K x 16 Static RAM
CY62147CV18LL-55BVI	CYPRESS	获取价格	256K x 16 Static RAM
CY62147CV18LL-70BAI	CYPRESS	获取价格	256K x 16 Static RAM
CY62147CV18LL-70BAIT	CYPRESS	获取价格	Standard SRAM, 256KX16, 70ns, CMOS, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, FBGA-48
CY62147CV18LL-70BVI	CYPRESS	获取价格	256K x 16 Static RAM

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