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CY621472GN30-45ZSXIT PDF预览

CY621472GN30-45ZSXIT

更新时间： 2024-11-20 14:56:35
品牌 Logo 应用领域
英飞凌 - INFINEON 静态存储器
页数 文件大小 规格书
20页 291K
描述
Asynchronous SRAM

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CY621472GN30-45ZSXIT 数据手册

 浏览型号CY621472GN30-45ZSXIT的Datasheet PDF文件第2页浏览型号CY621472GN30-45ZSXIT的Datasheet PDF文件第3页浏览型号CY621472GN30-45ZSXIT的Datasheet PDF文件第4页浏览型号CY621472GN30-45ZSXIT的Datasheet PDF文件第5页浏览型号CY621472GN30-45ZSXIT的Datasheet PDF文件第6页浏览型号CY621472GN30-45ZSXIT的Datasheet PDF文件第7页 
CY62147GN/CY621472GN MoBL®  
4-Mbit (256K words × 16 bit) Static RAM  
4-Mbit (256K words  
× 16 bit) Static RAM  
Features  
Functional Description  
■ High speed: 45 ns/55 ns  
CY62147GN and CY621472GN are high-performance CMOS  
low-power (MoBL) SRAM devices organized as 256K Words by  
16-bits. Both devices are offered in single and dual chip enable  
options and in multiple pin configurations.  
■ Ultra-low standby power  
❐ Typical standby current: 3.5 A  
❐ Maximum standby current: 8.7 A  
Devices with a single chip enable input are accessed by  
■ Widevoltage range: 1.65 V to2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V  
■ 1.0-V data retention  
asserting the chip enable (CE) input LOW. Dual chip enable  
devices are accessed by asserting both chip enable inputs – CE1  
as low and CE2 as HIGH.  
■ TTL-compatible inputs and outputs  
Data writes are performed by asserting the Write Enable (WE)  
input LOW, while providing the data on I/O0 through I/O15 and  
address on A0 through A17 pins. The Byte High Enable (BHE)  
and Byte Low Enable (BLE) inputs control write operations to the  
upper and lower bytes of the specified memory location. BHE  
controls I/O8 through I/O15 and BLE controls I/O0 through I/O7.  
■ Pb-free 48-ball VFBGA and 44-pin TSOP II packages  
Data reads are performed by asserting the Output Enable (OE)  
input and providing the required address on the address lines.  
Read data is accessible on the I/O lines (I/O0 through I/O15).  
Byte accesses can be performed by asserting the required byte  
enable signal (BHE or BLE) to read either the upper byte or the  
lower byte of data from the specified address location.  
All I/Os (I/O0 through I/O15) are placed in a HI-Z state when the  
device is deselected (CE HIGH for a single chip enable device  
and CE1 HIGH/CE2 LOW for a dual chip enable device), or  
control signals are de-asserted (OE, BLE, BHE).  
The device also has a unique Byte Power down feature, where,  
if both the Byte Enables (BHE and BLE) are disabled, the  
devices seamlessly switch to standby mode irrespective of the  
state of the chip enables, thereby saving power.  
The logic block diagram is provided in page 2.  
Product Portfolio  
Power Dissipation  
Features and  
Options  
(see the Pin  
Configurations  
section)  
Operating ICC, (mA)  
Standby, ISB2 (µA)  
Product  
Range  
VCC Range (V) Speed (ns)  
f = fmax  
Typ[1]  
Max  
Typ[1]  
Max  
CY62147GN18  
Industrial  
1.65 V–2.2 V  
2.2 V–3.6 V  
55  
45  
15  
15  
20  
20  
3.5  
3.5  
10  
Single or dual  
Chip Enables  
CY62147GN30  
CY621472GN30  
8.7  
CY62147GN  
4.5 V–5.5 V  
Notes  
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for a V range of 1.65 V–2.2 V),  
CC  
CC  
V
= 3 V (for V range of 2.2 V–3.6 V), and V = 5 V (for V range of 4.5 V–5.5 V), T = 25 °C.  
CC  
CC  
CC  
CC  
A
Cypress Semiconductor Corporation  
Document Number: 002-10624 Rev. *D  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised December 21, 2017  
1234567...20

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