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CY62136CV30LL-70BVXI PDF预览

CY62136CV30LL-70BVXI

更新时间: 2024-02-09 08:09:41
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
12页 306K
描述
2-Mbit (128K x 16) Static RAM

CY62136CV30LL-70BVXI 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:VFBGA,针数:48
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.79
最长访问时间:70 nsJESD-30 代码:R-PBGA-B48
JESD-609代码:e1长度:8 mm
内存密度:2097152 bit内存集成电路类型:STANDARD SRAM
内存宽度:16功能数量:1
端子数量:48字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128KX16封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:1 mm
最大供电电压 (Vsup):3.3 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
宽度:6 mmBase Number Matches:1

CY62136CV30LL-70BVXI 数据手册

 浏览型号CY62136CV30LL-70BVXI的Datasheet PDF文件第2页浏览型号CY62136CV30LL-70BVXI的Datasheet PDF文件第3页浏览型号CY62136CV30LL-70BVXI的Datasheet PDF文件第4页浏览型号CY62136CV30LL-70BVXI的Datasheet PDF文件第5页浏览型号CY62136CV30LL-70BVXI的Datasheet PDF文件第6页浏览型号CY62136CV30LL-70BVXI的Datasheet PDF文件第7页 
CY62136CV30 MoBL®  
2-Mbit (128K x 16) Static RAM  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that significantly  
reduces power consumption by 80% when addresses are not  
toggling. The device can also be put into standby mode  
reducing power consumption by more than 99% when  
deselected (CE HIGH). The input/output pins (I/O0 through  
Features  
• Very high speed  
— 55 ns  
• Voltage range  
— 2.7V – 3.3V  
I/O15) are placed in a high-impedance state when: deselected  
• Pin-compatible with the CY62136V  
• Ultra-low active power  
(CE HIGH), outputs are disabled (OE HIGH), both Byte High  
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),  
or during a write operation (CE LOW, and WE LOW).  
— Typical active current: 1.5 mA @ f = 1 MHz  
— Typical active current: 7 mA @ f = fMax (55 ns speed)  
• Low standby power  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A16). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A16).  
• Easy memory expansion with CE and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Available in Pb-free and non Pb-free 48-ball VFBGA  
package  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
Functional Description[1]  
The CY62136CV30 is high-performance CMOS static RAM  
organized as 128K words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
128K x 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
A3  
A2  
A1  
A0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05199 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 19, 2006  

CY62136CV30LL-70BVXI 替代型号

型号 品牌 替代类型 描述 数据表
CY62136CV30LL-70BVI CYPRESS

完全替代

2M (128K x 16) Static RAM

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