Datasheet > CY62136EV30LL

CY62136EV30LL

更新时间： 2024-01-26 00:56:02

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	563K
描述
2-Mbit (128K x 16) Static RAM

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CY62136EV30LL 数据手册

CY62136EV30

MoBL^®

2-Mbit (128K x 16) Static RAM

Features

Functional Description^[1]

• Very high speed: 45 ns

The CY62136EV30 is a high-performance CMOS static RAM

organized as 128K words by 16 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL^®) in

portable applications such as cellular telephones. The device

also has an automatic power-down feature that significantly

reduces power consumption by 80% when addresses are not

toggling. The device can also be put into standby mode

reducing power consumption by more than 99% when

deselected (CE HIGH). The input/output pins (I/O₀through

I/O₁₅) are placed in a high-impedance state when: deselected

(CE HIGH), outputs are disabled (OE HIGH), both Byte High

Enable and Byte Low Enable are disabled (BHE, BLE HIGH),

or during a write operation (CE LOW and WE LOW).

• Wide voltage range: 2.20V–3.60V

• Pin-compatible with CY62136CV30

• Ultra low standby power

— Typical standby current: 1µA

— Maximum standby current: 7µA

• Ultra-low active power

— Typical active current: 2 mA @ f = 1 MHz

• Easy memory expansion with CE, and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇), is

written into the location specified on the address pins (A₀

through A₁₆). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O₈through I/O₁₅) is written into the location

specified on the address pins (A₀through A₁₆).

• Offered in a Pb-free 48-ball VFBGA and 44-pin TSOP II

packages

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O₀to I/O₇. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O₈to I/O₁₅. See

the truth table at the back of this data sheet for a complete

description of read and write modes.

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A₉

A₈

A₇

A₆

A₅

A₄

A₃

A₂

128K x 16

RAM Array

I/O₀–I/O₇

I/O₈–I/O₁₅

A₁

A₀

COLUMN DECODER

BHE

BLE

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05569 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 6, 2006

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与CY62136EV30LL相关器件

型号	品牌	获取价格	描述	数据表
CY62136EV30LL-45BVXI	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62136EV30LL-45BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62136EV30LL-45BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62136EV30LL-45ZSXI	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62136EV30LL-45ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY62136EV30LL-45ZSXIT	CYPRESS	获取价格	Standard SRAM, 128KX16, 45ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62136EV30LL-45ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY62136FV30	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62136FV30_09	CYPRESS	获取价格	2 Mbit (128K x 16) Static RAM
CY62136FV30_11	CYPRESS	获取价格	2-Mbit (128 K x 16) Static RAM Automatic power down when deselected

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