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CY62136ESL-45ZSXI PDF预览

CY62136ESL-45ZSXI

更新时间: 2024-11-17 14:56:47
品牌 Logo 应用领域
英飞凌 - INFINEON 静态存储器
页数 文件大小 规格书
17页 446K
描述
Asynchronous SRAM

CY62136ESL-45ZSXI 数据手册

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CY62136ESL MoBL®  
2-Mbit (128 K × 16) Static RAM  
2-Mbit (128  
K × 16) Static RAM  
not toggling. Placing the device into standby mode reduces  
power consumption by more than 99% when deselected (CE  
HIGH). The input and output pins (I/O0 through I/O15) are placed  
in a high impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), both Byte High  
Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or  
during a write operation (CE LOW and WE LOW).  
Features  
Very high speed: 45 ns  
Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V  
Ultra low standby power  
Typical standby current: 1 A  
Maximum standby current: 7 A  
To write to the device, take Chip Enable (CE) and Write Enable  
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data  
from I/O pins (I/O0 through I/O7) is written into the location  
specified on the address pins (A0 through A16). If Byte High  
Enable (BHE) is LOW, then data from I/O pins (I/O8 through  
I/O15) is written into the location specified on the address pins  
(A0 through A16).  
Ultra low active power  
Typical active current: 2 mA at f = 1 MHz  
Easy memory expansion with CE and OE features  
Automatic power-down when deselected  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If  
Byte Low Enable (BLE) is LOW, then data from the memory  
location specified by the address pins appears on I/O0 to I/O7. If  
Byte High Enable (BHE) is LOW, then data from memory  
appears on I/O8 to I/O15. See the Truth Table on page 11 for a  
complete description of read and write modes.  
Complementary metal oxide semiconductor (CMOS) for  
optimum speed and power  
Available in Pb-free 44-pin thin small outline package (TSOP) II  
package  
Functional Description  
The device is suitable for interfacing with processors that have  
TTL I/P levels. It is not suitable for processors that require CMOS  
I/P levels. Please see Electrical Characteristics on page 4 for  
more details and suggested alternatives.  
The CY62136ESL is a high performance CMOS static RAM  
organized as 128K words by 16 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life(MoBL®) in portable  
applications. The device also has an automatic power down  
feature that reduces power consumption when addresses are  
For a complete list of related documentation, click here.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
128 K x 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
A1  
A0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Cypress Semiconductor Corporation  
Document Number: 001-48147 Rev. *L  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised November 29, 2017  

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