Datasheet > CY62136EV30_11

CY62136EV30_11

更新时间： 2024-09-30 09:42:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
15页	493K
描述
2-Mbit (128K x 16) Static RAM

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CY62136EV30_11 数据手册

CY62136EV30 MoBL^®

2-Mbit (128K x 16) Static RAM

Features

Functional Description

■ Very high speed: 45 ns

The CY62136EV30^[1]is a high performance CMOS static RAM

organized as 128 K words by 16 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL^®) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption when addresses are not toggling. The device can

also be put into standby mode reducing power consumption by

more than 99% when deselected (CE HIGH). The input/output

pins (I/O₀through I/O₁₅) are placed in a high impedance state

when: deselected (CE HIGH), outputs are disabled (OE HIGH),

both Byte High Enable and Byte Low Enable are disabled (BHE,

BLE HIGH), or during a write operation (CE LOW and WE LOW).

■ Wide voltage range: 2.20 V to 3.60 V

■ Pin compatible with CY62136CV30

■ Ultra low standby power

❐ Typical standby current: 1 A

❐ Maximum standby current: 7 A

■ Ultra low active power

❐ Typical active current: 2 mA at f = 1 MHz

■ Easy memory expansion with CE and OE features

■ Automatic power down when deselected

Writing to the device is accomplished by taking Chip Enable (CE)

and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is

LOW, then data from I/O pins (I/O₀through I/O₇), is written into

the location specified on the address pins (A₀through A₁₆). If

Byte High Enable (BHE) is LOW, then data from I/O pins (I/O₈

through I/O₁₅) is written into the location specified on the address

pins (A₀through A₁₆).

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed/power

■ Offered in a Pb-free 48-ball very fine ball grid array (VFBGA)

and 44-pin thin small outline package (TSOP II) packages

Reading from the device is accomplished by taking Chip Enable

(CE) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data

from the memory location specified by the address pins appear

on I/O₀to I/O₇. If Byte High Enable (BHE) is LOW, then data from

memory appear on I/O₈to I/O₁₅. See the Truth Table on page 10

for a complete description of read and write modes.

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A₉

A₈

A₇

A₆

A₅

A₄

A₃

A₂

128K x 16

RAM Array

I/O₀–I/O₇

I/O₈–I/O₁₅

A₁

A₀

COLUMN DECODER

BHE

BLE

Note

1. For best practice recommendations, refer to the Cypress application note “SRAM System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05569 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 17, 2011

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与CY62136EV30_11相关器件

型号	品牌	获取价格	描述	数据表
CY62136EV30_1106	CYPRESS	获取价格	2-Mbit (128 K x 16) Static RAM Automatic power down when deselected
CY62136EV30LL	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62136EV30LL-45BVXI	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62136EV30LL-45BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62136EV30LL-45BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62136EV30LL-45ZSXI	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM
CY62136EV30LL-45ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY62136EV30LL-45ZSXIT	CYPRESS	获取价格	Standard SRAM, 128KX16, 45ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62136EV30LL-45ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY62136FV30	CYPRESS	获取价格	2-Mbit (128K x 16) Static RAM

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