5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> CY62136CV30LL-70BVXIT
CY62136CV30LL-70BVXIT PDF预览

CY62136CV30LL-70BVXIT

更新时间： 2024-11-16 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
13页 216K
描述
Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48

阅读下载

中文翻译

获取价格

CY62136CV30LL-70BVXIT 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：VFBGA,针数：48
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.79
最长访问时间：70 nsJESD-30 代码：R-PBGA-B48
JESD-609代码：e1长度：8 mm
内存密度：2097152 bit内存集成电路类型：STANDARD SRAM
内存宽度：16功能数量：1
端子数量：48字数：131072 words
字数代码：128000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：128KX16封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：1 mm
最大供电电压 (Vsup)：3.3 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
宽度：6 mmBase Number Matches：1

CY62136CV30LL-70BVXIT 数据手册

 浏览型号CY62136CV30LL-70BVXIT的Datasheet PDF文件第2页浏览型号CY62136CV30LL-70BVXIT的Datasheet PDF文件第3页浏览型号CY62136CV30LL-70BVXIT的Datasheet PDF文件第4页浏览型号CY62136CV30LL-70BVXIT的Datasheet PDF文件第5页浏览型号CY62136CV30LL-70BVXIT的Datasheet PDF文件第6页浏览型号CY62136CV30LL-70BVXIT的Datasheet PDF文件第7页 
CY62136CV30/33 MoBL  
CY62136CV MoBL  
2M (128K x 16) Static RAM  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that significantly  
reduces power consumption by 80% when addresses are not  
toggling. The device can also be put into standby mode  
reducing power consumption by more than 99% when  
deselected (CE HIGH). The input/output pins (I/O0 through  
Features  
• Very high speed: 55 ns and 70 ns  
• Voltage range:  
— CY62136CV30: 2.7V–3.3V  
— CY62136CV33: 3.0V–3.6V  
— CY62136CV: 2.7V–3.6V  
I/O15) are placed in a high-impedance state when: deselected  
(CE HIGH), outputs are disabled (OE HIGH), both Byte High  
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),  
or during a write operation (CE LOW, and WE LOW).  
• Pin-compatible with the CY62136V  
• Ultra-low active power  
— Typical active current: 1.5 mA @ f = 1 MHz  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A16). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A16).  
— Typical active current: 5.5 mA @ f = fmax (70-ns  
speed)  
• Low standby power  
• Easy memory expansion with CE and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Packages offered in a 48-ball FBGA  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
Functional Description[1]  
The and CY62136CV are high-performance CMOS static  
RAM organized as 128K words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
Logic Block Diagram  
DATA IN DRIVERS  
A
10  
A
9
A
8
7
6
A
A
A
A
A
128K x 16  
5
4
RAM Array  
I/O –I/O  
0
7
2048 x 1024  
3
2
I/O –I/O  
A
8
15  
A
A
1
0
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05199 Rev. *D  
Revised September 20, 2002  
1234567...13

中文翻译

下载PDF

与CY62136CV30LL-70BVXIT相关器件

型号 品牌 获取价格 描述 数据表
CY62136CV33 CYPRESS

获取价格

 		2M (128K x 16) Static RAM
CY62136CV33LL-55BAI CYPRESS

获取价格

 		2M (128K x 16) Static RAM
CY62136CV33LL-55BAIT CYPRESS

获取价格

 		Standard SRAM, 128KX16, 55ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48
CY62136CV33LL-55BVI CYPRESS

获取价格

 		2M (128K x 16) Static RAM
CY62136CV33LL-70BAI CYPRESS

获取价格

 		2M (128K x 16) Static RAM
CY62136CV33LL-70BVI CYPRESS

获取价格

 		2M (128K x 16) Static RAM
CY62136CV33LL-70BVIT CYPRESS

获取价格

 		Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48
CY62136CVLL-70BAI CYPRESS

获取价格

 		2M (128K x 16) Static RAM
CY62136CVLL-70BAIT CYPRESS

获取价格

 		Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48
CY62136CVLL-70BVI CYPRESS

获取价格

 		2M (128K x 16) Static RAM

与CY62136CV30LL-70BVXIT相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证