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CY62126DV30LL-55BVXI PDF预览

CY62126DV30LL-55BVXI

更新时间： 2024-01-17 00:10:26
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
12页 364K
描述
1-Mbit (64K x 16) Static RAM

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中文翻译

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CY62126DV30LL-55BVXI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
针数：48Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：5.72
Is Samacsys：N最长访问时间：55 ns
I/O 类型：COMMONJESD-30 代码：R-PBGA-B48
JESD-609代码：e4长度：8 mm
内存密度：1048576 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：48
字数：65536 words字数代码：64000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：64KX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装等效代码：TSOP44,.46,32
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.5/3.3 V认证状态：Not Qualified
座面最大高度：1 mm最大待机电流：0.000003 A
最小待机电流：1.5 V子类别：SRAMs
最大压摆率：0.01 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.2 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：BALL端子节距：0.75 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：6 mmBase Number Matches：1

CY62126DV30LL-55BVXI 数据手册

 浏览型号CY62126DV30LL-55BVXI的Datasheet PDF文件第2页浏览型号CY62126DV30LL-55BVXI的Datasheet PDF文件第3页浏览型号CY62126DV30LL-55BVXI的Datasheet PDF文件第4页浏览型号CY62126DV30LL-55BVXI的Datasheet PDF文件第5页浏览型号CY62126DV30LL-55BVXI的Datasheet PDF文件第6页浏览型号CY62126DV30LL-55BVXI的Datasheet PDF文件第7页 
CY62126DV30 MoBL®  
1-Mbit (64K x 16) Static RAM  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that significantly  
reduces power consumption by 90% when addresses are not  
toggling. The device can be put into standby mode reducing  
power consumption by more than 99% when deselected (CE  
HIGH). The input/output pins (I/O0 through I/O15) are placed  
in a high-impedance state when: deselected (CE HIGH),  
outputs are disabled (OE HIGH), both Byte High Enable and  
Byte Low Enable are disabled (BHE, BLE HIGH) or during a  
write operation (CE LOW and WE LOW).  
Features  
• Very high speed  
— 55 ns  
• Temperature Ranges  
— Industrial: –40°C to 85°C  
— Automotive: –40°C to 125°C  
• Wide voltage range  
— 2.2V - 3.6V  
• Pin compatible with CY62126BV  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A15).  
• Ultra-low active power  
— Typical active current: 0.85 mA @ f = 1 MHz  
— Typical active current: 5 mA @ f = fMax (55 ns speed)  
• Ultra-low standby power  
• Easy memory expansion with CE and OE features  
• Automatic power-down when deselected  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
• Available in Pb-free and non Pb-free 48-ball VFBGA and  
44-pin TSOP Type II packages  
Functional Description[1]  
The CY62126DV30 is a high-performance CMOS static RAM  
organized as 64K words by 16 bits. This device features  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
64K x 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
A1  
A0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05230 Rev. *H  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 18, 2006  
[+] Feedback  
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中文翻译

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CY62126DV30LL-55BVXI 替代型号

型号 品牌 替代类型 描述 数据表
CY62127DV30LL-55ZXI CYPRESS

功能相似

 1-Mb (64K x 16) Static RAM
CY62126DV30LL-55ZI CYPRESS

功能相似

 1-Mbit (64K x 16) Static RAM

与CY62126DV30LL-55BVXI相关器件

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CY62126DV30LL-55LFXI CYPRESS

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 		Standard SRAM, 64KX16, 55ns, CMOS, 8 X 8 MM, LEAD FREE, QFN-56
CY62126DV30LL-55ZI ROCHESTER

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 		64KX16 STANDARD SRAM, 55ns, PDSO44, TSOP2-44
CY62126DV30LL-55ZI CYPRESS

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 		1-Mbit (64K x 16) Static RAM
CY62126DV30LL-55ZIT CYPRESS

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 		Standard SRAM, 64KX16, 55ns, CMOS, PDSO44, TSOP2-44
CY62126DV30LL-55ZSI CYPRESS

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 		1-Mbit (64K x 16) Static RAM
CY62126DV30LL-55ZSXI CYPRESS

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 		1-Mbit (64K x 16) Static RAM
CY62126DV30LL-55ZXI CYPRESS

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 		1-Mbit (64K x 16) Static RAM
CY62126DV30LL-55ZXI ROCHESTER

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 		64KX16 STANDARD SRAM, 55ns, PDSO44, LEAD FREE, TSOP2-44
CY62126DV30LL-55ZXIT CYPRESS

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 		Standard SRAM, 64KX16, 55ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62126DV30LL-70BVI CYPRESS

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 		1-Mbit (64K x 16) Static RAM

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