Datasheet > CY62126DV30LL-55LFXI

CY62126DV30LL-55LFXI

更新时间： 2024-01-21 07:15:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
13页	250K
描述
Standard SRAM, 64KX16, 55ns, CMOS, 8 X 8 MM, LEAD FREE, QFN-56

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CY62126DV30

MoBL^®

1-Mbit (64K x 16) Static RAM

This is ideal for providing More Battery Life™ (MoBL^®) in

portable applications such as cellular telephones. The device

also has an automatic power-down feature that significantly

reduces power consumption by 90% when addresses are not

toggling. The device can be put into standby mode reducing

power consumption by more than 99% when deselected (CE

HIGH). The input/output pins (I/O₀through I/O₁₅) are placed

in a high-impedance state when: deselected (CE HIGH),

outputs are disabled (OE HIGH), both Byte High Enable and

Byte Low Enable are disabled (BHE, BLE HIGH) or during a

write operation (CE LOW and WE LOW).

Features

• Temperature Ranges

— Industrial: –40°C to 85°C

— Automotive: –40°C to 125°C

• Very high speed: 45 ns

• Wide voltage range: 2.2V to 3.6V

• Pin compatible with CY62126BV

• Ultra-low active power

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇), is

written into the location specified on the address pins (A₀

through A₁₅). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O₈through I/O₁₅) is written into the location

specified on the address pins (A₀through A₁₅).

— Typical active current: 0.85 mA @ f = 1 MHz

— Typical active current: 5 mA @ f = f_MAX

• Ultra-low standby power

• Easy memory expansion with CE and OE features

• Automatic power-down when deselected

• Packages offered in a 48-ball FBGA, 56-lead QFN and

a 44-lead TSOP Type II

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O₀to I/O₇. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O₈to I/O₁₅. See

the truth table at the back of this data sheet for a complete

description of read and write modes.

• Also available in Lead-free packages

Functional Description^[1]

The CY62126DV30 is a high-performance CMOS static RAM

organized as 64K words by 16 bits. This device features

advanced circuit design to provide ultra-low active current.

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A₉

A₈

A₇

A₆

A₅

A₄

A₃

A₂

64K x 16

RAM Array

2048 x 512

I/O₀–I/O₇

I/O₈–I/O₁₅

A₁

A₀

COLUMN DECODER

BHE

BLE

Note:

1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05230 Rev. *G

• 3901 North First Street

• San Jose, CA 95134

• 408-943-2600

Revised May 30, 2005

12 3 4 5 6 7...13

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与CY62126DV30LL-55LFXI相关器件

型号	品牌	获取价格	描述	数据表
CY62126DV30LL-55ZI	ROCHESTER	获取价格	64KX16 STANDARD SRAM, 55ns, PDSO44, TSOP2-44
CY62126DV30LL-55ZI	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126DV30LL-55ZIT	CYPRESS	获取价格	Standard SRAM, 64KX16, 55ns, CMOS, PDSO44, TSOP2-44
CY62126DV30LL-55ZSI	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126DV30LL-55ZSXI	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126DV30LL-55ZXI	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126DV30LL-55ZXI	ROCHESTER	获取价格	64KX16 STANDARD SRAM, 55ns, PDSO44, LEAD FREE, TSOP2-44
CY62126DV30LL-55ZXIT	CYPRESS	获取价格	Standard SRAM, 64KX16, 55ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62126DV30LL-70BVI	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126DV30LL-70BVI	ROCHESTER	获取价格	64KX16 STANDARD SRAM, 70ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48

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