是否Rohs认证: | 符合 | 生命周期: | Obsolete |
零件包装代码: | QFP | 包装说明: | FQFP, |
针数: | 208 | Reach Compliance Code: | unknown |
HTS代码: | 8542.39.00.01 | 风险等级: | 5.75 |
其他特性: | ALSO OPERATES WITH 3.3V SUPPLY VOLTAGE | JESD-30 代码: | S-PQFP-G208 |
JESD-609代码: | e3/e4 | 长度: | 28 mm |
专用输入次数: | I/O 线路数量: | 136 | |
端子数量: | 208 | 最高工作温度: | 70 °C |
最低工作温度: | 组织: | 0 DEDICATED INPUTS, 136 I/O | |
输出函数: | MACROCELL | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | FQFP | 封装形状: | SQUARE |
封装形式: | FLATPACK, FINE PITCH | 峰值回流温度(摄氏度): | 260 |
可编程逻辑类型: | LOADABLE PLD | 传播延迟: | 10 ns |
认证状态: | Not Qualified | 座面最大高度: | 3.77 mm |
最大供电电压: | 2.7 V | 最小供电电压: | 2.3 V |
标称供电电压: | 2.5 V | 表面贴装: | YES |
技术: | CMOS | 温度等级: | COMMERCIAL |
端子面层: | MATTE TIN/NICKEL PALLADIUM GOLD | 端子形式: | GULL WING |
端子节距: | 0.5 mm | 端子位置: | QUAD |
处于峰值回流温度下的最长时间: | 20 | 宽度: | 28 mm |
Base Number Matches: | 1 |
型号 | 品牌 | 替代类型 | 描述 | 数据表 |
CY39100V208B-83NTXC | CYPRESS |
完全替代 ![]() |
Loadable PLD, 15ns, CMOS, PQFP208, 28 X 28 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, EQFP-208 |
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CY39100V208B-125NTC | CYPRESS |
完全替代 ![]() |
Loadable PLD, 10ns, 1536-Cell, CMOS, PQFP208, 28 X 28 MM, 0.50 MM PITCH, PLASTIC, EQFP-208 |
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型号 | 品牌 | 获取价格 | 描述 | 数据表 |
CY39100V208B-200NTC | ROCHESTER |
获取价格 |
LOADABLE PLD, 7.5 ns, PQFP208, 28 X 28 MM, 0.50 MM PITCH, PLASTIC, EQFP-208 |
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CY39100V208B-83NTXC | CYPRESS |
获取价格 |
Loadable PLD, 15ns, CMOS, PQFP208, 28 X 28 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, EQFP-208 |
![]() |
CY39100V256-125BBI | CYPRESS |
获取价格 |
Loadable PLD, 10ns, CMOS, PBGA256, 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-256 |
![]() |
CY39100V256-125MBC | CYPRESS |
获取价格 |
CPLDs at FPGA Densities |
![]() |
CY39100V256-125MGC | CYPRESS |
获取价格 |
CPLDs at FPGA Densities |
![]() |
CY39100V256-181BBC | CYPRESS |
获取价格 |
CPLDs at FPGA Densities |
![]() |
CY39100V256-181MBC | CYPRESS |
获取价格 |
CPLDs at FPGA Densities |
![]() |
CY39100V256-181MGC | CYPRESS |
获取价格 |
CPLDs at FPGA Densities |
![]() |
CY39100V256-181NC | CYPRESS |
获取价格 |
CPLDs at FPGA Densities |
![]() |
CY39100V256-200MGC | CYPRESS |
获取价格 |
CPLDs at FPGA Densities |
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