Delta39K™ ISR™
CPLD Family
PRELIMINARY
CPLDs at FPGA Densities™
•Multiple I/O standards supported
Features
— LVCMOS, LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II),
HSTL (I-IV), and GTL+
•High density
— 15K to 350K usable gates
— 256 to 5376 macrocells
— 92 to 520 maximum I/O pins
•Compatible with NOBL™, ZBT™, and QDR™ SRAMs
•Programmable slew rate control on each I/O pin
•User-Programmable Bus Hold capability on each I/O pin
•Fully PCI compliant (to 66 MHz 64-bit PCI spec rev2.2)
•Compact PCI hot swap compatible
•Multiple package/pinout offering across all densities
— 144 to 676 pins in PQFP, BGA and FBGA packages
— Same pinout for 3.3V/2.5V and 1.8V devices
— Simplifies design migration across density
— Self-Boot™ solution in BGA and FBGA packages
•In-System Reprogrammable™ (ISR™)
— 12 Dedicated Inputs including 4 clock pins, 4 global
control signal pins and 4 JTAG interface pins for
reconfigurability
•Embedded Memory
— 40K to 840K bits embedded SRAM
• 32K to 672K bits of (single port) Cluster memory
• 8K to 168K bits of (dual port) Channel memory
•High speed - 250 MHz in-system operation
•AnyVolt™ interface
JTAG-compliant on-board programming
—
— 3.3V, 2.5V and 1.8V V versions available
CC
— Design changes don’t cause pinout changes
•IEEE1149.1 JTAG boundary scan
— 3.3V, 2.5V and 1.8V I/O capability on all versions
• Low Power Operation
0.18- m 6-layer metal SRAM-based logic process
—
µ
Development Software
— Full-CMOS implementation of product term array
Standby current as low as 100 A at 1.8V V
—
µ
•Warp™
CC
•Simple timing model
— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing.
— No penalty for using full 16 product terms / macrocell
— No delay for single product term steering or sharing
•Flexible clocking
— Active-HDL FSM graphical finite state machine editor
— Active-HDL SIM post-synthesis timing simulator
— Architecture Explorer for detailed design analysis
— Static Timing Analyzer for critical path analysis
— Available on Windows 95, 98 & NT for $99
— 4 synchronous clocks per device
— 1 spread-aware PLL drives all 4 clock networks
— Locally generated Product Term clock
— Clock polarity control at each register
•Carry chain logic for fast efficient arithmetic operations
— Supports all Cypress Programmable Logic Products
Delta39K™ ISR CPLD Family Members
[1]
Standby I
CC
Cluster
Channel
f
Speed-t
PD
T =25 C
°
MAX2
A
Typical
Gates
memory memory Maximum
Pin-to-Pin
(ns)
Device
39K15
Macrocells
256
(Kbits)
(Kbits)
I/O Pins
(MHz)
250
222
222
200
181
167
167
154
3.3/2.5V
1.8V
8K–24K
16K–48K
32
8
134
6.5
7.0
7.0
7.5
8.0
8.5
8.5
9.0
10 mA
10 mA
10 mA
10 mA
10 mA
10 mA
10 mA
10 mA
100 µA
200 µA
300 µA
600 µA
1000 µA
1250 µA
1500 µA
2100 µA
39K30
512
64
16
176
39K50
23K–72K
768
96
24
218
39K100
39K165
39K200
39K250
39K350
46K–144K
77K–241K
92K–288K
115K–361K
161K–505K
1536
2560
3072
3840
5376
192
320
384
480
672
48
302
80
386
96
428
120
168
470
520
Note:
1. Standby ICC values are with PLL not utilized, no output load and stable inputs
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
August 9, 2000
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