Datasheet > CY39100V256B-83BBC

CY39100V256B-83BBC

更新时间： 2024-02-17 21:03:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		输入元件可编程逻辑
页数	文件大小	规格书
7页	94K
描述
Loadable PLD, 15ns, 1536-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FBGA-256

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CY39100V256B-83BBC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LBGA, BGA256,16X16,40
针数：	256	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	Factory Lead Time：	1 week
风险等级：	5.81	其他特性：	ALSO OPERATES WITH 3.3V SUPPLY VOLTAGE
系统内可编程：	YES	JESD-30 代码：	S-PBGA-B256
JESD-609代码：	e0	JTAG BST：	YES
长度：	17 mm	湿度敏感等级：	3
专用输入次数：		I/O 线路数量：	180
宏单元数：	1536	端子数量：	256
最高工作温度：	70 °C	最低工作温度：
组织：	0 DEDICATED INPUTS, 180 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA256,16X16,40	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE	峰值回流温度（摄氏度）：	225
电源：	1.5/3.3,2.5/3.3 V	可编程逻辑类型：	LOADABLE PLD
传播延迟：	15 ns	认证状态：	Not Qualified
座面最大高度：	1.6 mm	子类别：	Programmable Logic Devices
最大供电电压：	2.7 V	最小供电电压：	2.3 V
标称供电电压：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	17 mm
Base Number Matches：	1

CY39100V256B-83BBC 数据手册

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Delta39K™ PLL and Clock Tree

The Delta39K PLL and the global clock tree provide design-

Introduction

ers with functionality that can be configured to meet various

design requirements. This functionality includes clock phase

adjustment, clock multiplication and division, Spread Aware™

feature, lock detection, off-chip clocking and buffering, and

JTAG support.

The purpose of this application note is to provide information

and instruction in utilizing the functionality of the Delta39K™

Phase-Locked Loop (PLL) and associated clock tree.

Delta39K is a family of high-density Complex Programmable

Logic Devices (CPLDs) containing on-chip components such

as Single-Port RAM, advanced Dual-Port RAM, and a PLL.

The Delta39K PLL can be used in any system requiring clock

frequency or clock phase manipulation.

Clock Phase Adjustment

Designers may use the PLL and clock tree to re-position the

edges of the PLL-generated clock in order to shift perfor-

mance toward either improved set-up time or improved

clock-to-out time. The clock's phase, or the position of its edg-

es relative to the PLL input, may be adjusted in either of two

ways: Skewing the clock moves its phase backward on the

time axis, while de-skewing the clock moves its phase fore-

word on the time axis.

For Delta39K, programming is defined as the loading of a

user’s design into the on-chip FLASH device internal to the

Delta39K package. Configuration, on the other hand, is the

loading of a user’s design into the volatile Delta39K die.

Overview of PLL & Clock Tree

Within each 3.3V/2.5V Delta39K device, a single on-chip PLL

resides as part of a larger clocking scheme. Four local dedi-

cated clock input pins, referred to here as GCLK[3:0], provide

direct inputs to this clock tree. GCLK[0] and GCLK[1] may

also be used as an input port and external feedback port,

respectively to the PLL. Within the clock tree are four global

clocks, referred to here as INTCLK[3:0], which are accessible

to any macrocell, I/O cell, or memory block. GCLK[3:0] and

the outputs of the PLL feed a set of multiplexors which source

INTCLK[3:0]. Figure 1 contains a block diagram of the clock

tree and PLL.

There are eight options for skewing the incoming clock. The

clock can be skewed so that the phase is delayed 0°, 45°, 90°,

135°, 180°, 225°, 270°, or 315°. A 45° phase shift increment

is equal to a delay of 1/8th of the clock's period length. Note

that adding delay to the incoming clock has the effect of in-

creasing effective clock-to-out time while decreasing the ef-

fective setup time requirements. Refer to Figure 2 for an ex-

ample.

Time when data

Time when new data

must be ready

reaches output pin

EXTERNAL

Off-chip clock

pll_in

t_P

t_S

t_CO

CLOCK_TREE

Delay

Any I/O Cell

Any Macrocell

Any Memory

DIRECT

Smaller

Larger

^effectivet_S

^effectivet_CO

Feedback

ext_fdbk

[1]

(clock to out time)

(setup time)

(1,2,4,8)

pll_in

gclk0

Source

Divide

t_SK

t_CO

gclk0-3

[0]

[3:0]

gclk1

gclk2

gclk3

135

180

225

270

315

Lock

Figure 2. Skewed Clock and Adjusted t_Sand t_CO

[0:3]

lock_detect

Figure 1. Delta39K Phase Locked Loop and Clock Tree.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

July 6, 2001

12 3 4 5 6 7

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CY39100V388-181NC	CYPRESS	CPLDs at FPGA Densities	获取价格
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