Datasheet > CY39100V484A-125BBC

CY39100V484A-125BBC

更新时间： 2024-09-14 20:03:03

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		输入元件可编程逻辑
页数	文件大小	规格书
3页	73K
描述
Loadable PLD, 10ns, 1536-Cell, CMOS, PBGA484, 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, TFBGA-484

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CY39100V484A-125BBC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, TFBGA-484
针数：	484	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.84
其他特性：	IT CAN ALSO HAVE AN INPUT VOLTAGE OF 3.3V	系统内可编程：	YES
JESD-30 代码：	S-PBGA-B484	JTAG BST：	YES
长度：	23 mm	专用输入次数：
I/O 线路数量：	302	宏单元数：	1536
端子数量：	484	最高工作温度：	70 °C
最低工作温度：		组织：	0 DEDICATED INPUTS, 302 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA484,22X22,40
封装形状：	SQUARE	封装形式：	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	1.5/3.3,2.5/3.3 V
可编程逻辑类型：	LOADABLE PLD	传播延迟：	10 ns
认证状态：	Not Qualified	座面最大高度：	1.6 mm
子类别：	Programmable Logic Devices	最大供电电压：	2.7 V
最小供电电压：	2.3 V	标称供电电压：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	23 mm
Base Number Matches：	1

CY39100V484A-125BBC 数据手册

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PRELIMINARY

Using the Delta39K™ ISR™ Prototype Board

Introduction

This application note is intended to provide instruction in the

use of the Delta39K™ ISR™ Prototype Board. This board

serves two major purposes. First, it provides a board with

Cypress Delta39K and Ultra37000™ CPLDs already con-

nected to take advantage of In-System Reprogrammability™

(ISR). This allows designers who are unfamiliar with ISR to

investigate it as a possible device programming solution.

Second, it permits designers who need custom logic to more

easily utilize Cypress CPLDs in prototype designs. After pro-

gramming the Delta39K and/or Ultra37000 devices on the

ISR Prototype Board, connections can be made between the

ISR Prototype Board and the designer’s board using the pro-

vided header strips. This gives a designer the ability to verify

the functionality of the CPLDs within a system before design-

ing them into that system.

D esign

Files

S ynthesis and Fitting

O utput D ata Files

(H E X / JE D )

This application note should familiarize the reader in the use

of the Delta39K ISR Prototype Board and highlight the

board’s features. Topics of discussion will include connecting

the programming cable, connecting power supplies to the

board, using the jumpers on the board, and making connec-

tions between the Delta39K ISR Prototype Board and other

systems.

S T AP L

C om poser

In-System Reprogrammability allows Complex Programma-

ble Logic Devices (CPLDs) to be reprogrammed after being

soldered in place on a printed circuit board. The Delta39K ISR

Prototype Board is designed to support one Delta39K and

Ultra37000 CPLD. The first device is a 100,000 gate 3.3V

Delta39K100 in a 208-pin PQFP package. The second device

is a 256 macrocell 3.3V Ultra37000 in a 160-pin TQFP pack-

age.

S T AP L P rogram m ing

Files

S T AP L

P layer

ISR programming of the CPLDs follows the IEEE 1149.1 stan-

dard Test Access Port and Boundary Scan architecture,

which supports chaining more than one IEEE1149.1/

JTAG -compliant devices together. ISR Programming Soft-

ware supports daisy-chain programming of multiple Cypress

CPLDs.

D elta39K / U ltra37000

D evice

Delta39K and Ultra37000 CPLDs support the STAPL stan-

dard as the solution for ISR programming. STAPL is an inter-

preted language that provides a standard for programming

PLDs through the JTAG interface. The CPLDs on the

Delta39K ISR Prototype Board are programmed through an

ISR cable using the Cypress ISR Programming Software. To

learn more about the ISR features of the Delta39K and

Ultra37000 family, refer to Cypress application notes at our

website (http://www.cypress.com/pld/pldappnotes.html)

Figure 1. Cypress CPLD Design Flow

synthesized into logic. Fitter software is responsible for map-

ping the logic into the targeted device. Both synthesis and

fitting are accomplished from the Warp™ environment. The

result of the fitting process is a compressed Intel Hex file

(Delta39K) or a JEDEC file (Ultra37000) that contains the in-

formation about how the logic of the design will be implement-

ed in the device. STAPL Composer software uses the output

files from Warp to produce STAPL standard programming

files. A STAPL file contains both the programming data and

programming algorithm for the device it targets. A STAPL

Player is then used to program the CPLDs using the STAPL

Design Flow

In order to use the Delta39K ISR Prototype Board, it is impor-

tant to understand how it fits into the ISR design flow. The

basic design flow for the Cypress CPLD is shown in Figure 1.

Designs are typically specified in VHDL or Verilog code. This

code can either be written by the designer or generated from

schematics. Once the code for the design is complete, it is

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

January 19, 2001

12 3

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与CY39100V484A-125BBC相关器件

型号	品牌	获取价格	描述	数据表
CY39100V484B-125BBC	CYPRESS	获取价格	Loadable PLD, 10ns, 1536-Cell, CMOS, PBGA484, 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA
CY39100V484B-125BBI	ROCHESTER	获取价格	LOADABLE PLD, 10ns, PBGA484, 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-484
CY39100V676-125MBI	CYPRESS	获取价格	Loadable PLD, 10ns, CMOS, PBGA676, 27 X 27 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-676
CY39100V676-83MBI	CYPRESS	获取价格	Loadable PLD, 15ns, CMOS, PBGA676, 27 X 27 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-676
CY39100V676A-200MBC	CYPRESS	获取价格	Loadable PLD, 7.5ns, 1536-Cell, CMOS, PBGA676, 27 X 27 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBG
CY39100V676B-125MBC	ROCHESTER	获取价格	LOADABLE PLD, 10 ns, PBGA676, 27 X 27 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-676
CY39100V676B-200MBC	CYPRESS	获取价格	Loadable PLD, 7.5ns, 1536-Cell, CMOS, PBGA676, 27 X 27 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBG
CY39100Z208-125BBC	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39100Z208-125BBI	CYPRESS	获取价格	CPLDs at FPGA Densities
CY39100Z208-125BGC	CYPRESS	获取价格	CPLDs at FPGA Densities

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