Delta39K PLL and Clock Tree
configurations any one of the eight division settings may be
individually selected for gclk[0-3].
Table 4. Valid Multiply & Divide Options: EXTERNAL
Selected
When the EXTERNAL feedback option is selected only mul-
tiplication by a factor of one and division by a factor of one
may be selected for the off-chip clock that is being used in the
feedback path. The other three PLL generated clocks may
use any of the eight division settings. Valid pll_in frequencies,
multiply and divide options for this configuration are detailed
in table 4.
Valid Multiply
Option
Valid Divide Option
pll_in
Freq
VCO
Freq[3]
(MHz) Value (MHz)
gclk0-3
Freq
Off-chip
Freq
Value
(MHz)
(MHz)
50-133
1
100-266
For Feedback Path
100-266 50-133
Note that if an on-chip clock is sent off-chip, it will be further
divided by two on top of any divide settings chosen
1
Multiplying an input frequency allows one to use slower fre-
quencies throughout the board (externally) and use faster fre-
quencies internally. (Assuming they are not needed other
places so as to make this less advantageous). This allows for
less power consumption, less electromagnetic interference
(EMI), and less undesirable high speed signal integrity is-
sues.
For Non-Feedback Path
1-6,8,16 6.25-266 3.125-133
Spread Aware™ Feature
The PLLs incorporated in all Delta39K CPLDs are Spread
Aware. This feature refers to the ability of the PLL to track a
spread-spectrum input clock such that its spread is seen on
the output clock. Spread-spectrum is a method of 'spreading'
or modulating a fundamental or original frequency in a con-
trolled, oscillatory manner, such that the electromagnetic en-
ergy broadcast at any given component in the frequency
spectrum is below the maximum value imposed by FCC reg-
ulations. Spread Aware does not mean that the PLL is capa-
ble of generating a spread-spectrum output from a non
spread-spectrum input.
Also, designs requiring a given throughput or bandwidth run-
ning at a lower frequency and wider bus-width, can be in-
creased to a higher frequency, while the bus-width can be
reduced to a narrower width. This way, less logic resources
(real estate) can be used on the Cypress CPLD, while main-
taining the same throughput.
Table 3. Valid Multiply & Divide Options: DIRECT or
CLOCK_TREE Selected
Valid Multiply
Option
Valid Divide Option
gclk0-3 Off-chip
When configured with a x1, x2 or x4 multiply option the
Delta39K PLL is Spread Aware whereas the x8 multiply op-
tion does not support the Spread Aware feature.
pll_in
Freq
VCO
Freq
(MHz)
Freq
Freq[2]
(MHz)
Designers may choose to use the spread aware Delta39K
PLL with a spread spectrum input clock. Down spread, up
spread, or some form of middle spread such as center spread
may be used on the incoming clock. However, the total
amount of spread in either or both directions should be limited
to 0.6% of the fundamental frequency. The modulation fre-
quency of the spread should be 50 kHz or less in order to
ensure that the PLL will meet the performance specified in the
data sheet and maintain its intended 1 MHz loop bandwidth.
Value
(MHz)
Value
(MHz)
N/A DC-12.5
N/A
N/A
DC-12.5 DC-6.25
8
4
2
1
12.5- 33 100-266 1-6,8,16 6.25-266 3.125-133
25-66 100-266 1-6,8,16 6.25-266 3.125-133
50-133 100-266 1-6,8,16 6.25-266 3.125-133
100-133 100-133 1-6,8,16 6.25-133 3.125-66
Lock Detection
A finite amount of time is required from the moment that the
incoming clock signal is placed on the GCLK[0] pin, and thus
drives the source of the PLL, to the time that the PLL actually
achieves steady-state operation, or lock. Designs that contain
logic that will not operate properly until a valid clock signal is
present at the output of the PLL, are dependent upon the PLL
first achieving lock. Designs such as these may require a sig-
nal to indicate when the PLL has reached lock. The PLL can
be configured to generate a lock detect signal at a dedicated
I/O pin. This pin is fed by a multiplexor that can be configured
to select either a general-purpose I/O function or a lock de-
tection indicator function for this pin.
N/A 133-fMAX
N/A
N/A
133-fMAX 66-fMAX
Notes:
2. An off-chip clock is the output of a toggle flip-flop, which acts as a /2.
3. When an off-chip clock is fed back to ext_fdbk, the toggle flip-flop is effectively placed into the feedback path, resultingin an implicit x2 on top of the x1 multiplication
setting.
3
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