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CY2SSTV857ZXI-27T PDF预览

CY2SSTV857ZXI-27T

更新时间: 2024-11-19 03:07:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟驱动器逻辑集成电路电视光电二极管双倍数据速率PC
页数 文件大小 规格书
9页 151K
描述
Differential Clock Buffer/Driver DDR333/PC2700-Compliant

CY2SSTV857ZXI-27T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:TSSOP
包装说明:TSSOP,针数:48
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.1Is Samacsys:N
系列:SSTV输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G48JESD-609代码:e4
长度:12.4965 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:48
实输出次数:10最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):7.5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.1 ns
座面最大高度:1.1 mm最大供电电压 (Vsup):2.63 V
最小供电电压 (Vsup):2.38 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:6.096 mm
最小 fmax:200 MHzBase Number Matches:1

CY2SSTV857ZXI-27T 数据手册

 浏览型号CY2SSTV857ZXI-27T的Datasheet PDF文件第2页浏览型号CY2SSTV857ZXI-27T的Datasheet PDF文件第3页浏览型号CY2SSTV857ZXI-27T的Datasheet PDF文件第4页浏览型号CY2SSTV857ZXI-27T的Datasheet PDF文件第5页浏览型号CY2SSTV857ZXI-27T的Datasheet PDF文件第6页浏览型号CY2SSTV857ZXI-27T的Datasheet PDF文件第7页 
CY2SSTV857-27  
Differential Clock Buffer/Driver  
DDR333/PC2700-Compliant  
Description  
Features  
• Operating frequency: 60 MHz to 200 MHz  
• Supports 266, 333-MHz DDR SDRAM  
• 10 differential outputs from 1 differential input  
• Spread-Spectrum-compatible  
• Low jitter (cycle-to-cycle): < 75  
• Very low skew: < 100 ps  
• Power management control input  
• High-impedance outputs when input clock < 10 MHz  
• 2.5V operation  
The CY2SSTV857-27 is a high-performance, low-skew,  
low-jitter zero-delay buffer designed to distribute differential  
clocks in high-speed applications. The CY2SSTV857-27  
generates ten differential pair clock outputs from one differ-  
ential pair clock input. In addition, the CY2SSTV857-27  
features differential feedback clock outputs and inputs. This  
allows the CY2SSTV857-27 to be used as a zero-delay buffer.  
When used as a zero-delay buffer in nested clock trees, the  
CY2SSTV857-27 locks onto the input reference and translates  
with near-zero delay to low-skew outputs.  
• Pin-compatible with CDC857-2 and -3  
• 48-pin TSSOP package  
• Industrial temp. of 40° to +85°C  
• Conforms to JEDEC DDR specification  
Block Diagram  
Pin Configuration  
3
2
Y0  
V S S  
Y 0 #  
Y 0  
V D D Q  
Y 1  
Y 1 #  
V S S  
V S S  
Y 2 #  
1
2
3
4
5
6
7
8
4 8  
4 7  
4 6  
4 5  
4 4  
4 3  
4 2  
4 1  
4 0  
3 9  
3 8  
3 7  
3 6  
3 5  
3 4  
3 3  
3 2  
3 1  
3 0  
2 9  
2 8  
2 7  
2 6  
2 5  
V S S  
Y 5 #  
Y 5  
V D D Q  
Y 6  
Y 6 #  
V S S  
V S S  
Y 7 #  
Y0#  
5
6
Y1  
Y1#  
Y2  
Y2#  
37  
T est and  
PD#  
Powerdown  
10  
9
16  
Logic  
AVDD  
20  
19  
Y3  
Y3#  
Y4  
Y4#  
22  
23  
9
Y 2  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Y 7  
46  
47  
V D D Q  
V D D Q  
C L K  
C LK #  
V D D Q  
A V D D  
A V S S  
V S S  
Y 3 #  
Y 3  
V D D Q  
Y 4  
Y 4 #  
V S S  
V D D Q  
P D #  
F B IN  
F B IN #  
V D D Q  
F B O U T #  
F B O U T  
V S S  
Y 8 #  
Y 8  
V D D Q  
Y 9  
Y 9 #  
V S S  
Y5  
Y5#  
Y6  
Y6#  
44  
43  
13  
14  
CLK  
39  
40  
Y7  
Y7#  
Y8  
Y8#  
CLK#  
PLL  
29  
30  
36  
35  
FBIN  
FBIN#  
27  
26  
Y9  
Y9#  
32  
33  
FBO UT  
FBO UT #  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07464 Rev. *G  
Revised January 25, 2005  

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