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CY2X013LXCXXXT PDF预览

CY2X013LXCXXXT

更新时间: 2024-11-23 06:51:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
7页 246K
描述
6-Pin Ceramic LCC SMD - Tape and Reel

CY2X013LXCXXXT 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:DLCC包装说明:LSON, SOLCC6,.12
针数:6Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.79其他特性:CAN ALSO OPERATES AT 3.3V SUPPLY
JESD-30 代码:R-CDSO-N6长度:5 mm
端子数量:6最高工作温度:70 °C
最低工作温度:最大输出时钟频率:690 MHz
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:LSON
封装等效代码:SOLCC6,.12封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, LOW PROFILE电源:2.5/3.3 V
认证状态:Not Qualified座面最大高度:1.3 mm
子类别:Clock Generators最大压摆率:125 mA
最大供电电压:2.625 V最小供电电压:2.375 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:1.27 mm
端子位置:DUAL宽度:3.2 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

CY2X013LXCXXXT 数据手册

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PRELIMINARY  
CY2X013  
LVDS Crystal Oscillator (XO)  
Features  
Functional Description  
Low Jitter Crystal Oscillator (XO)  
The CY2X013 is a high performance and high frequency Crystal  
Oscillator (XO). The device uses a Cypress proprietary low noise  
PLL to synthesize the frequency from an integrated crystal.  
Less than 1 ps Typical RMS Phase Jitter  
LVDS Output  
The CY2X013 is available as a factory configured device or as a  
field programmable device.  
Output Frequency from 50 MHz to 690 MHz  
Factory Configured or Field Programmable  
Integrated Phase-Locked Loop (PLL)  
Output Enable or Power Down Function  
Supply Voltage: 3.3V or 2.5V  
Pb-free Package: 5.0 x 3.2 mm LCC  
Commercial and Industrial Temperature Ranges  
Logic Block Diagram  
4
CRYSTAL  
OSCILLATOR  
LOW-NOISE  
CLK  
PLL  
OUTPUT  
DIVIDER  
5
CLK#  
PROGRAMMABLE  
CONFIGURATION  
1
OE/PD#  
6
3
VDD  
VSS  
Pinout  
Figure 1. Pin Diagram - 6-Pin Ceramic LCC  
OE/PD# 1  
DNU 2  
6 VDD  
5 CLK#  
4 CLK  
VSS 3  
Table 1. Pin Definitions - 6-Pin Ceramic LCC  
Pin  
Name  
I/O Type  
Description  
1
OE/PD#  
CMOS Input Output Enable Pin: Active HIGH. If OE = 1, CLK is enabled.  
Power Down Pin: Active LOW. If PD# = 0, the device is powered down and the clock is disabled.  
The functionality of this pin is programmable  
4, 5  
2
6
CLK, CLK# LVDS Output Differential Output Clock  
DNU  
VDD  
VSS  
Do Not Use: DNU pins are electrically connected, but perform no function  
Supply Voltage: 2.5V or 3.3V  
Ground  
Power  
Power  
3
Cypress Semiconductor Corporation  
Document Number: 001-10261 Rev. *B  
198 Champion Court  
San Jose  
,
CA 95134-1709  
408-943-2600  
Revised June 15, 2009  
[+] Feedback  

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