Datasheet > CY28RS480-1

CY28RS480-1

更新时间： 2024-02-05 01:37:29

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器
页数	文件大小	规格书
16页	232K
描述
Clock Generator for ATI RS480 Chipset

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中文翻译

获取价格

数据手册

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CY28RS480-1 数据手册

PRELIMINARY

CY28RS480-1

Clock Generator for ATI^RS480 Chipset

• 66-MHz HyperTransport clock

Features

• I²C support with readback capabilities

• Supports AMD^CPU

• Ideal Lexmark Spread Spectrum profile for maximum

• Selectable CPU frequencies

• 200-MHz differential CPU clock pairs

• 100-MHz differential SRC clocks

• 48-MHz USB clock

electromagnetic interference (EMI) reduction

• 3.3V power supply

• 56-pin SSOP and TSSOP packages

CPU

SRC

HTT66

PCI

REF

x 3

USB_48

x 1

• 33-MHz PCI clock

Block Diagram

Pin Configuration

VDD_REF

REF[0:2]

XIN

XTAL

OSC

XOUT

PLL Ref Freq

XIN

XOUT

VDD_REF

VSS_REF

REF0

VDD_CPU

CPUT[0:2], CPUC[0:2],

VDD_48

USB_48

VSS_48

CLK_STOP

SCLK

Divider

CPU_STP#

CLKREQ[0:1]#

PLL1

Network

REF1

VDD_SRC

SRCT[0:6],SRCC[0:6]

REF2

VDD_PCI

PCI0

VDD_SRCS

SRCST[0:1],SRCSC[0:1]

IREF

SDATA

VSS_PCI

VDD_HTT

HTT66

VDD_PCI

PCI

CLKREQ#0

CLKREQ#1

SRCT5

VSS_HTT

CPUT0

CPUC0

VDD_CPU

VSS_CPU

CPUT1

CPUC1

VDDA

VDD_HTT

HTT66

SRCC5

VDD_SRC

VSS_SRC

SRCT4

VDD_48 MHz

SRCC4

PLL2

SRCT3

USB_48

SRCC3

VSSA

VSS_SRC

VDD_SRC

SRCT2

IREF

VSS_SRC

VDD_SRC

SRCT0

SRCC0

SRCC2

SRCT1

SRCC1

VDD_SRC1

VSS_SRC1

SRCST0

VSS_SRC

SRCST1

SRCSC1

SDATA

SCLK

I C

Logic

SRCSC0

56 SSOP/TSSOP

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07714 Rev. *C

Revised August 4, 2005

12 3 4 5 6 7...16

中文翻译

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