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CY28RS480ZXCT PDF预览

CY28RS480ZXCT

更新时间: 2024-11-01 22:08:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
15页 218K
描述
Clock Generator for ATI RS480 Chipset

CY28RS480ZXCT 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:TSSOP包装说明:6 X 12 MM, LEAD FREE, MO-153, TSSOP2-56
针数:56Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.44Is Samacsys:N
JESD-30 代码:R-PDSO-G56JESD-609代码:e4
长度:13.9955 mm湿度敏感等级:3
端子数量:56最高工作温度:70 °C
最低工作温度:最大输出时钟频率:200 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP56,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V主时钟/晶体标称频率:14.31818 MHz
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Clock Generators最大压摆率:450 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:6.096 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

CY28RS480ZXCT 数据手册

 浏览型号CY28RS480ZXCT的Datasheet PDF文件第2页浏览型号CY28RS480ZXCT的Datasheet PDF文件第3页浏览型号CY28RS480ZXCT的Datasheet PDF文件第4页浏览型号CY28RS480ZXCT的Datasheet PDF文件第5页浏览型号CY28RS480ZXCT的Datasheet PDF文件第6页浏览型号CY28RS480ZXCT的Datasheet PDF文件第7页 
CY28RS480  
Clock Generator for ATIRS480 Chipset  
• I2C support with readback capabilities  
Features  
• Ideal Lexmark Spread Spectrum profile for maximum  
• Supports AMDCPU  
electromagnetic interference (EMI) reduction  
• 200-MHz differential CPU clock pairs  
• 100-MHz differential SRC clocks  
• 48-MHz USB clock  
• 33-MHz PCI clock  
• 66-MHz HyperTransportclock  
• 3.3V power supply  
• 56-pin SSOP and TSSOP packages  
CPU  
x2  
SRC  
x8  
HTT66  
x1  
PCI  
x1  
REF  
x 3  
USB_48  
x 1  
Block Diagram  
Pin Configuration  
VDD_REF  
REF[0:2]  
XIN  
XOUT  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
VDD_REF  
VSS_REF  
REF0  
XIN  
XTAL  
OSC  
2
XOUT  
PLL Ref Freq  
VDD_48  
USB_48  
VSS_48  
NC  
3
VDD_CPU  
CPUT[0:1], CPUC[0:1],  
4
REF1  
Divider  
CPU_STP#  
CLKREQ[0:1]#  
PLL1  
5
REF2  
Network  
VDD_SRC  
SRCT[0:5],SRCC[0:5]  
6
VDD_PCI  
PCI0  
SCLK  
7
VDD_SRCS  
SDATA  
8
VSS_PCI  
VDD_HTT  
HTT66  
SRCST[0:1],SRCSC[0:1]  
NC  
9
IREF  
PD  
CLKREQ#0  
CLKREQ#1  
SRCT5  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
VDD_PCI  
PCI  
VSS_HTT  
CPUT0  
CPUC0  
VDD_CPU  
VSS_CPU  
CPUT1  
CPUC1  
VDDA  
VDD_HTT  
HTT66  
SRCC5  
VDD_SRC  
VSS_SRC  
SRCT4  
VDD_48 MHz  
SRCC4  
SRCT3  
PLL2  
USB_48  
SRCC3  
VSS_SRC  
VDD_SRC  
SRCT2  
VSSA  
IREF  
VSS_SRC1  
VDD_SRC1  
SRCT0  
SRCC2  
SRCT1  
SRCC0  
SRCC1  
VSS_SRC  
SRCST1  
SRCSC1  
VDD_SRCS  
VSS_SRCS  
SRCST0  
2
SDATA  
SCLK  
I C  
Logic  
SRCSC0  
56 SSOP/TSSOP  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07638 Rev. *C  
Revised February 21, 2005  

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