Datasheet > CY28RS600

CY28RS600

更新时间： 2024-11-02 04:38:03

品牌	Logo	应用领域
SPECTRALINEAR		时钟发生器
页数	文件大小	规格书
17页	208K
描述
Clock Generator for ATI RS5XX, 6XX Chipsets

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数据手册

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CY28RS600 数据手册

CY28RS600

Clock Generator for ATI^£ꢀRS5XX, 6XX Chipsets

• 48 MHz USB clock

• I²C support with readback capabilities

Features

• Supports Intel^£CPU

• Ideal Lexmark Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• 3.3V power supply

• Selectable CPU frequencies

• Differential CPU clock pairs (30% over/10%under

clocked)

• 64-pin TSSOP packages

• 100 MHz differential ATI Graphics clocks (100%

over/10% under clocked)

CPU

SRC

ATIG

REF

x 3

USB_48

x 2

• 100 MHz differential SRC clocks (10% over/under

clocked)

Block Diagram

Pin Configuration

VDD_REF

XIN

VSS_REF

FSA_REF0

FSB_REF1

FSC_REF2

RESET_IN#

CPU_STOP#

CPUT0

VDD

XIN

14.318MHz

Crystal

XOUT

REF[0:2]

XOUT

PLL Reference

Divider

VDD48

USB48_0

USB48_1

VSS48

VDD_CPU

CPUT[0:2]

CPUC[0:2]

CPU

PLL

VTTPWRGD#/PD

SCLK

CPUC0

CLKREQ# [C:A]

RESET_IN#

VDD_CPU

VSS_CPU

CPUT1

SDATA

CLKREQA#

SRCT7

FS[C:A]

CPUC1

VDD_ATIG

ATIGT[0:3]

ATIGC[0:3]

SRCC7

CPUT2

SRC

PLL

Divider

VDD_SRC

VSS_SRC

SRCT6

CPUC2

VDDA

VSSA

SRCC6

VSSSRC

SRCT0

SRCT5

VDD_SRC

SRCT[0:7]

SRCC[0:7]

SRCC5

SRCC0

SRC

PLL

SRCT4_SATAT

SRCC4_SATAC

VSS_SRC

VDD_SRC

SRCT3

VSS_SRC

VDD_SRC

ATIGT0

Divider

ATIGC0

ATIGT1

VDD48

SRCC3

ATIGC1

Fixed

PLL

USB48[1:0]

SRCT2

VDD_ATIG

VSS_ATIG

ATIGT2

SRCC2

VDD_SRC

VSS_SRC

SRCT1

VTT_PWRGD#/PD

ATIGC2

I2C

Logic

SDATA

SCLK

ATIGT3

SRCC1

ATIGC3

CLKREQB#

CLKREQC#

64 TSSOP

Rev 1.0, November 22, 2006

2200 Laurelwood Road, Santa Clara, CA 95054

Page 1 of 17

www.SpectraLinear.com

Tel:(408) 855-0555 Fax:(408) 855-0550

12 3 4 5 6 7...17

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