CY15B004J
then wait for an acknowledge from the master. If the
acknowledge occurs, the CY15B004J will transfer the next
sequential byte. If the acknowledge is not sent, the CY15B004J
will end the read operation. For a write operation, the
CY15B004J will accept 8 data bits from the master then send an
acknowledge. All data transfer occurs MSB (most significant bit)
first.
Slave Device Address
The first byte that the CY15B004J expects after a START
condition is the slave address. As shown in Figure 6, the slave
address contains the device type or slave ID, the device select
address bits, a page select bit, and a bit that specifies if the
transaction is a read or a write.
Bits 7–4 are the device type (slave ID) and should be set to
1010b for the CY15B004J. These bits allow other function types
to reside on the I2C bus within an identical address range. Bits
3–2 are the device select address bits. They must match the
corresponding value on the external address pins to select the
device. Up to four CY15B004J devices can reside on the same
I2C bus by assigning a different address to each. Bit 1 is the page
select bit. It specifies the 256-byte block of memory that is
targeted for the current operation. Bit 0 is the read/write bit
(R/W). R/W = ‘1’ indicates a read operation and R/W = ‘0’
indicates a write operation.
Memory Operation
The CY15B004J is designed to operate in a manner very similar
to other I2C interface memory products. The major differences
result from the higher performance write capability of F-RAM
technology. These improvements result in some differences
between the CY15B004J and a similar configuration EEPROM
during writes. The complete operation for both writes and reads
is explained below.
Write Operation
All writes begin with a slave address, then a word address. The
bus master indicates a write operation by setting the LSB of the
slave address (R/W bit) to a ‘0’. After addressing, the bus master
sends each byte of data to the memory and the memory
generates an acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range is reached
internally, the address counter will wrap from 1FFh to 000h.
Figure 6. Memory Slave Device Address
handbook, halfpMagSe B
LSB
1
A2 A1
0
A0 R/W
1
0
Page
select
Device
Select
Slave ID
Unlike other nonvolatile memory technologies, there is no
effective write delay with F-RAM. Since the read and write
access times of the underlying memory are the same, the user
experiences no delay through the bus. The entire memory cycle
occurs in less time than a single bus clock. Therefore, any
operation including read or write can occur immediately following
a write. Acknowledge polling, a technique used with EEPROMs
to determine if a write is complete is unnecessary and will always
return a ready condition.
Addressing Overview (Word Address)
After the CY15B004J (as receiver) acknowledges the slave
address, the master can place the word address on the bus for
a write operation. The word address is the lower 8-bits of the
address to be combined with the 1-bit page select to specify
exactly the byte to be written. The complete 9-bit address is
latched internally. No word address occurs for a read operation.
Reads always use the lower 8-bits that are held internally in the
address latch and the 9th address bit is part of the slave address.
Reads always begin at the address following the previous
access. A random read address can be loaded by doing a write
operation as explained below.
Internally, an actual memory write occurs after the 8th data bit is
transferred. It will be complete before the acknowledge is sent.
Therefore, if the user desires to abort a write without altering the
memory contents, this should be done using START or STOP
condition prior to the 8th data bit. The CY15B004J uses no page
buffering.
After transmission of each data byte, just prior to the
acknowledge, the CY15B004J increments the internal address
latch. This allows the next sequential byte to be accessed with
no additional addressing. After the last address (1FFh) is
reached, the address latch will roll over to 000h. There is no limit
to the number of bytes that can be accessed with a single read
or write operation.
The memory array can be write-protected using the WP pin.
Setting the WP pin to a HIGH condition (VDD) will write-protect
all addresses. The CY15B004J will not acknowledge data bytes
that are written to protected addresses. In addition, the address
counter will not increment if writes are attempted to these
addresses. Setting WP to a LOW state (VSS) will disable the write
protect. WP is pulled down internally.
Data Transfer
After the address bytes have been transmitted, data transfer
between the bus master and the CY15B004J can begin. For a
read operation the CY15B004J will place 8 data bits on the bus
Figure 7 and Figure 8 on page 7 below illustrate a single-byte
and multiple-byte write cycles.
Figure 7. Single-Byte Write
Start
S
Address & Data
Stop
By Master
Slave Address
0
A
Word Address
A
Data Byte
A
P
By F-RAM
Acknowledge
Document Number: 002-10549 Rev. *C
Page 6 of 18
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