Datasheet > CY14B101Q1_11

CY14B101Q1_11

更新时间： 2024-09-28 09:40:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
26页	1161K
描述
1 Mbit (128 K x 8) Serial SPI nvSRAM Infinite read, write, and RECALL cycles

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中文翻译

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数据手册

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CY14B101Q1_11 数据手册

CY14B101Q1

CY14B101Q2

CY14B101Q3

1 Mbit (128 K x 8) Serial SPI nvSRAM

❐ 8-pin dual flat no-lead (DFN) package and 16-pin small

outline integrated circuit (SOIC) package

Features

❐ Restriction of hazardous substances (RoHS) compliant

■ 1-Mbit nonvolatile static random access memory (nvSRAM)

❐ Internally organized as 128 K × 8

❐ STORE to QuantumTrap nonvolatile elements initiated

automatically on power-down (AutoStore) or by user using

HSB pin (Hardware STORE) or SPI instruction (Software

STORE)

❐ RECALL to SRAM initiated on power-up

(Power-Up RECALL) or by SPI instruction

(Software RECALL)

Functional Overview

The

Cypress

CY14B101Q1/CY14B101Q2/CY14B101Q3

combines a 1 Mbit nvSRAM with a nonvolatile element in each

memory cell with serial SPI interface. The memory is organized

as 128 K words of 8 bits each. The embedded nonvolatile

elements incorporate the QuantumTrap technology, creating the

world’s most reliable nonvolatile memory. The SRAM provides

infinite read and write cycles, while the QuantumTrap cell

provides highly reliable nonvolatile storage of data. Data

transfers from SRAM to the nonvolatile elements (STORE

operation) takes place automatically at power-down (except for

CY14B101Q1). On power-up, data is restored to the SRAM from

the nonvolatile memory (RECALL operation). Both STORE and

RECALL operations can also be initiated by the user through SPI

instruction.

❐ Automatic STORE on power-down with a small capacitor

(except for CY14B101Q1)

■ High reliability

❐ Infinite read, write, and RECALL cycles

❐ 1 million STORE cycles to QuantumTrap

❐ Data retention: 20 years

■ High speed serial peripheral interface (SPI)

❐ 40 MHz clock rate

❐ Supports SPI mode 0 (0,0) and mode 3 (1,1)

Configuration

Feature

CY14B101Q1

CY14B101Q2

CY14B101Q3

■ Write protection

AutoStore

Yes

❐ Hardware protection using Write Protect (WP) pin

❐ Software protection using Write Disable instruction

❐ Software block protection for 1/4,1/2, or entire array

Software

STORE

Yes

Hardware

STORE

Yes

■ Low power consumption

❐ Single 3 V +20%, –10% operation

❐ Average active current of 10 mA at 40 MHz operation

■ Industry standard configurations

❐ Industrial temperature

❐ CY14B101Q1 has identical pin configuration to industry

standard 8-pin NV memory

Logic Block Diagram

V_CC

V_CAP

QuantumTrap

128 K X 8

Power Control

SCK

Instruction decode

Write protect

Control logic

STORE/RECALL

Control

STORE

HSB

SRAM Array

128 K X 8

HOLD

RECALL

Instruction

D0-D7

A0-A16

Address

Decoder

Data I/O register

Status Register

Cypress Semiconductor Corporation

Document #: 001-50091 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 18, 2011

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与CY14B101Q1_11相关器件

型号	品牌	获取价格	描述	数据表
CY14B101Q1_13	CYPRESS	获取价格	1-Mbit (128 K x 8) Serial SPI nvSRAM
CY14B101Q1A-S104XI	CYPRESS	获取价格	Non-Volatile SRAM, 128KX8, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, MS-012, SOIC-8
CY14B101Q1A-SXI	CYPRESS	获取价格	1-Mbit (128 K x 8) Serial (SPI) nvSRAM Data r
CY14B101Q1A-SXIT	CYPRESS	获取价格	1-Mbit (128 K x 8) Serial (SPI) nvSRAM Data r
CY14B101Q1-LHXC	CYPRESS	获取价格	1 Mbit (128K x 8) Serial SPI nvSRAM
CY14B101Q1-LHXCT	CYPRESS	获取价格	1 Mbit (128K x 8) Serial SPI nvSRAM
CY14B101Q1-LHXI	CYPRESS	获取价格	1 Mbit (128K x 8) Serial SPI nvSRAM
CY14B101Q1-LHXIT	CYPRESS	获取价格	1 Mbit (128K x 8) Serial SPI nvSRAM
CY14B101Q2	CYPRESS	获取价格	1 Mbit (128K x 8) Serial SPI nvSRAM
CY14B101Q2A-S104XI	CYPRESS	获取价格	Non-Volatile SRAM, 128KX8, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, MS-012, SOIC-8

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