Datasheet > 存储 > SRAM> CY14B101Q2-LHXC

CY14B101Q2-LHXC

更新时间： 2024-01-19 02:26:52

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
22页	1399K
描述
1 Mbit (128K x 8) Serial SPI nvSRAM

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中文翻译

获取价格

数据手册

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CY14B101Q2-LHXC 数据手册

CY14B101Q1

CY14B101Q2

CY14B101Q3

PRELIMINARY

1 Mbit (128K x 8) Serial SPI nvSRAM

■ Low Power Consumption

❐ Single 3V +20%, –10% operation

❐ Average V_CCcurrent of 10 mA at 40 MHz operation

Features

■ 1 Mbit Nonvolatile SRAM

❐ Internally organized as 128K x 8

■ Industry Standard Configurations

❐ Commercial and industrial temperatures

❐ CY14B101Q1 has identical pin configuration to industry stan-

dard 8-pin NV Memory

❐ 8-pin DFN and 16-pin SOIC Packages

❐ RoHS compliant

❐ STORE to QuantumTrap nonvolatile elements initiated auto-

matically on power down (AutoStore) or by user using HSB

pin (Hardware Store) or SPI instruction (Software Store)

❐ RECALL to SRAM initiated on power up (Power Up Recall)

or by SPI Instruction (Software RECALL)

❐ Automatic STORE on power down with a small capacitor

■ High Reliability

Functional Overview

❐ Infinite Read, Write, and RECALLl cycles

❐ 200,000 STORE cycles to QuantumTrap

❐ Data Retention: 20 Years

The

Cypress

CY14B101Q1/CY14B101Q2/CY14B101Q3

combines a 1 Mbit nonvolatile static RAM with a nonvolatile

element in each memory cell. The memory is organized as 128K

words of 8 bits each. The embedded nonvolatile elements incor-

porate the QuantumTrap technology, creating the world’s most

reliable nonvolatile memory. The SRAM provides infinite read

and write cycles, while the QuantumTrap cell provides highly

reliable nonvolatile storage of data. Data transfers from SRAM to

the nonvolatile elements (STORE operation) takes place

automatically at power down. On power up, data is restored to

the SRAM from the nonvolatile memory (RECALL operation).

Both STORE and RECALL operations can also be triggered by

the user.

■ High Speed Serial Peripheral Interface (SPI)

❐ 40 MHz Clock rate

❐ Supports SPI Modes 0 (0,0) and 3 (1,1)

■ Write Protection

❐ Hardware Protection using Write Protect (WP) Pin

❐ Software Protection using Write Disable Instruction

❐ Software Block Protection for 1/4,1/2, or entire Array

V_CC

V_CAP

Logic Block Diagram

Quantum Trap

128K X 8

Power Control

SCK

Instruction decode

Write protect

Control logic

STORE/RECALL

Control

STORE

HSB

SRAM ARRAY

HOLD

RECALL

128K X 8

Instruction

D0-D7

A0-A16

Address

Decoder

Data I/O register

Status register

Cypress Semiconductor Corporation

Document #: 001-50091 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 02, 2009

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与CY14B101Q2-LHXC相关器件

型号	品牌	获取价格	描述	数据表
CY14B101Q2-LHXCT	CYPRESS	获取价格	1 Mbit (128K x 8) Serial SPI nvSRAM
CY14B101Q2-LHXI	CYPRESS	获取价格	1 Mbit (128K x 8) Serial SPI nvSRAM
CY14B101Q2-LHXI	INFINEON	获取价格	nvSRAM (non-volatile SRAM)
CY14B101Q2-LHXIT	CYPRESS	获取价格	1 Mbit (128K x 8) Serial SPI nvSRAM
CY14B101Q2-LHXIT	INFINEON	获取价格	nvSRAM (non-volatile SRAM)
CY14B101Q3	CYPRESS	获取价格	1 Mbit (128K x 8) Serial SPI nvSRAM
CY14B101Q3A-SF104XIT	CYPRESS	获取价格	Non-Volatile SRAM, 128KX8, CMOS, PDSO16, 0.300 INCH, ROHS COMPLIANT, MO-119, SOIC-16
CY14B101Q3-SFXC	CYPRESS	获取价格	1 Mbit (128K x 8) Serial SPI nvSRAM
CY14B101Q3-SFXCT	CYPRESS	获取价格	1 Mbit (128K x 8) Serial SPI nvSRAM
CY14B101Q3-SFXI	CYPRESS	获取价格	1 Mbit (128K x 8) Serial SPI nvSRAM

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