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CY14B101Q3-SFXCT PDF预览

CY14B101Q3-SFXCT

更新时间: 2024-11-23 06:51:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
22页 1399K
描述
1 Mbit (128K x 8) Serial SPI nvSRAM

CY14B101Q3-SFXCT 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.4
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.42Is Samacsys:N
JESD-30 代码:R-PDSO-G16长度:10.2865 mm
内存密度:1048576 bit内存集成电路类型:NON-VOLATILE SRAM
内存宽度:8功能数量:1
端子数量:16字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:SERIAL峰值回流温度(摄氏度):260
电源:3/3.3 V认证状态:Not Qualified
座面最大高度:2.336 mm最大待机电流:0.005 A
子类别:SRAMs最大压摆率:0.01 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.49 mmBase Number Matches:1

CY14B101Q3-SFXCT 数据手册

 浏览型号CY14B101Q3-SFXCT的Datasheet PDF文件第2页浏览型号CY14B101Q3-SFXCT的Datasheet PDF文件第3页浏览型号CY14B101Q3-SFXCT的Datasheet PDF文件第4页浏览型号CY14B101Q3-SFXCT的Datasheet PDF文件第5页浏览型号CY14B101Q3-SFXCT的Datasheet PDF文件第6页浏览型号CY14B101Q3-SFXCT的Datasheet PDF文件第7页 
CY14B101Q1  
CY14B101Q2  
CY14B101Q3  
PRELIMINARY  
1 Mbit (128K x 8) Serial SPI nvSRAM  
Low Power Consumption  
Single 3V +20%, –10% operation  
Average VCC current of 10 mA at 40 MHz operation  
Features  
1 Mbit Nonvolatile SRAM  
Internally organized as 128K x 8  
Industry Standard Configurations  
Commercial and industrial temperatures  
CY14B101Q1 has identical pin configuration to industry stan-  
dard 8-pin NV Memory  
8-pin DFN and 16-pin SOIC Packages  
RoHS compliant  
STORE to QuantumTrap nonvolatile elements initiated auto-  
matically on power down (AutoStore) or by user using HSB  
pin (Hardware Store) or SPI instruction (Software Store)  
RECALL to SRAM initiated on power up (Power Up Recall)  
or by SPI Instruction (Software RECALL)  
Automatic STORE on power down with a small capacitor  
High Reliability  
Functional Overview  
Infinite Read, Write, and RECALLl cycles  
200,000 STORE cycles to QuantumTrap  
Data Retention: 20 Years  
The  
Cypress  
CY14B101Q1/CY14B101Q2/CY14B101Q3  
combines a 1 Mbit nonvolatile static RAM with a nonvolatile  
element in each memory cell. The memory is organized as 128K  
words of 8 bits each. The embedded nonvolatile elements incor-  
porate the QuantumTrap technology, creating the world’s most  
reliable nonvolatile memory. The SRAM provides infinite read  
and write cycles, while the QuantumTrap cell provides highly  
reliable nonvolatile storage of data. Data transfers from SRAM to  
the nonvolatile elements (STORE operation) takes place  
automatically at power down. On power up, data is restored to  
the SRAM from the nonvolatile memory (RECALL operation).  
Both STORE and RECALL operations can also be triggered by  
the user.  
High Speed Serial Peripheral Interface (SPI)  
40 MHz Clock rate  
Supports SPI Modes 0 (0,0) and 3 (1,1)  
Write Protection  
Hardware Protection using Write Protect (WP) Pin  
Software Protection using Write Disable Instruction  
Software Block Protection for 1/4,1/2, or entire Array  
VCC  
VCAP  
Logic Block Diagram  
Quantum Trap  
128K X 8  
Power Control  
CS  
WP  
SCK  
Instruction decode  
Write protect  
Control logic  
STORE/RECALL  
Control  
STORE  
HSB  
SRAM ARRAY  
HOLD  
RECALL  
128K X 8  
Instruction  
register  
D0-D7  
A0-A16  
Address  
Decoder  
Data I/O register  
Status register  
SO  
SI  
Cypress Semiconductor Corporation  
Document #: 001-50091 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 02, 2009  
[+] Feedback  

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