Datasheet > CY14B101Q1_10

CY14B101Q1_10

更新时间： 2024-01-28 09:51:53

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
24页	908K
描述
1 Mbit (128K x 8) Serial SPI nvSRAM

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中文翻译

获取价格

数据手册

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CY14B101Q1_10 数据手册

CY14B101Q1

CY14B101Q2

CY14B101Q3

1 Mbit (128K x 8) Serial SPI nvSRAM

Features

Functional Overview

The

Cypress

CY14B101Q1/CY14B101Q2/CY14B101Q3

■

1 Mbit Nonvolatile SRAM

combines a 1 Mbit nonvolatile static RAM with a nonvolatile

element in each memory cell. The memory is organized as 128K

words of 8 bits each. The embedded nonvolatile elements incor-

porate the QuantumTrap technology, creating the world’s most

reliable nonvolatile memory. The SRAM provides infinite read

and write cycles, while the QuantumTrap cell provides highly

reliable nonvolatile storage of data. Data transfers from SRAM to

the nonvolatile elements (STORE operation) takes place

automatically at power down. On power up, data is restored to

the SRAM from the nonvolatile memory (RECALL operation).

Both STORE and RECALL operations can also be triggered by

the user.

❐

Internally organized as 128K x 8

❐

STORE to QuantumTrap Nonvolatile Elements initiated au-

tomatically on Power Down(AutoStore)orby userusing HSB

Pin (Hardware Store) or SPI instruction (Software Store)

RECALL to SRAM initiated on Power Up (Power Up Recall)

or by SPI Instruction (Software RECALL)

❐

Automatic STORE on Power Down with a small Capacitor

■

High Reliability

❐

Infinite Read, Write, and RECALL Cycles

1 Million STORE cycles to QuantumTrap

Data Retention: 20 Years

Configuration

■

High Speed Serial Peripheral Interface (SPI)

❐

40 MHz Clock Rate

Feature

CY14B101Q1

CY14B101Q2

CY14B101Q3

❐

Supports SPI Modes 0 (0,0) and 3 (1,1)

AutoStore

Yes

Write Protection

Software

STORE

Yes

❐

Hardware Protection using Write Protect (WP) Pin

Software Protection using Write Disable Instruction

Software Block Protection for 1/4,1/2, or entire Array

Hardware

STORE

Yes

■

Low Power Consumption

❐

Single 3V +20%, –10% Operation

❐

Average V_CCcurrent of 10 mA at 40 MHz Operation

Industry Standard Configurations

❐

Industrial Temperature

❐

CY14B101Q1 has identical pin configuration to industry stan-

dard 8-pin NV Memory

❐

8-pin DFN and 16-pin SOIC Packages

RoHS Compliant

V_CC

V_CAP

Logic Block Diagram

Quantum Trap

Power Control

128K X 8

SCK

Instruction decode

Write protect

Control logic

STORE/RECALL

Control

STORE

HSB

SRAM ARRAY

HOLD

RECALL

128K X 8

Instruction

D0-D7

A0-A16

Address

Decoder

Data I/O register

Status register

Cypress Semiconductor Corporation

Document #: 001-50091 Rev. *D

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised January 04, 2010

12 3 4 5 6 7...24

中文翻译

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与CY14B101Q1_10相关器件

型号	品牌	获取价格	描述	数据表
CY14B101Q1_11	CYPRESS	获取价格	1 Mbit (128 K x 8) Serial SPI nvSRAM Infinite read, write, and RECALL cycles
CY14B101Q1_13	CYPRESS	获取价格	1-Mbit (128 K x 8) Serial SPI nvSRAM
CY14B101Q1A-S104XI	CYPRESS	获取价格	Non-Volatile SRAM, 128KX8, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, MS-012, SOIC-8
CY14B101Q1A-SXI	CYPRESS	获取价格	1-Mbit (128 K x 8) Serial (SPI) nvSRAM Data r
CY14B101Q1A-SXIT	CYPRESS	获取价格	1-Mbit (128 K x 8) Serial (SPI) nvSRAM Data r
CY14B101Q1-LHXC	CYPRESS	获取价格	1 Mbit (128K x 8) Serial SPI nvSRAM
CY14B101Q1-LHXCT	CYPRESS	获取价格	1 Mbit (128K x 8) Serial SPI nvSRAM
CY14B101Q1-LHXI	CYPRESS	获取价格	1 Mbit (128K x 8) Serial SPI nvSRAM
CY14B101Q1-LHXIT	CYPRESS	获取价格	1 Mbit (128K x 8) Serial SPI nvSRAM
CY14B101Q2	CYPRESS	获取价格	1 Mbit (128K x 8) Serial SPI nvSRAM

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