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CP3CN17K38Y PDF预览

CP3CN17K38Y

更新时间: 2024-11-04 22:40:59
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
220页 3172K
描述
Reprogrammable Connectivity Processor with CAN Interface

CP3CN17K38Y 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:CSP-48Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.31.00.01
风险等级:5.83地址总线宽度:
位大小:16边界扫描:YES
最大时钟频率:12 MHz外部数据总线宽度:
格式:FIXED POINT集成缓存:YES
JESD-30 代码:S-XQCC-N48JESD-609代码:e4
长度:7 mm低功率模式:YES
湿度敏感等级:3端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:QCCN
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):235认证状态:Not Qualified
座面最大高度:1.1 mm速度:24 MHz
最大供电电压:2.75 V最小供电电压:2.25 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Gold (Ni/Au)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

CP3CN17K38Y 数据手册

 浏览型号CP3CN17K38Y的Datasheet PDF文件第2页浏览型号CP3CN17K38Y的Datasheet PDF文件第3页浏览型号CP3CN17K38Y的Datasheet PDF文件第4页浏览型号CP3CN17K38Y的Datasheet PDF文件第5页浏览型号CP3CN17K38Y的Datasheet PDF文件第6页浏览型号CP3CN17K38Y的Datasheet PDF文件第7页 
FINAL  
APRIL 2005  
CP3CN17 Reprogrammable Connectivity Processor  
with CAN Interface  
1.0 General Description  
The CP3CN17 connectivity processor combines a powerful The CP3CN17 is backed up by the software resources de-  
RISC core with on-chip SRAM and Flash memory for high signers need for rapid time-to-market, including an operat-  
computing bandwidth, hardware communications peripher- ing system, peripheral drivers, reference designs, and an  
als for high I/O bandwidth, and an external bus for system integrated development environment.  
expandability.  
National Semiconductor offers a complete and industry-  
On-chip communications peripherals include: CAN control- proven application development environment for CP3CN17  
ler, ACCESS.bus, Microwire/Plus, SPI, UART, and Ad- applications, including the IAR Embedded Workbench,  
vanced Audio Interface (AAI). Additional on-chip peripherals iSYSTEM winIDEA and iC3000 Active Emulator, Develop-  
include DMA controller, CVSD/PCM conversion module, ment Board, and Application Software.  
Timing and Watchdog Unit, Versatile Timer Unit, Multi-  
Function Timer, and Multi-Input Wakeup.  
Block Diagram  
Clock Generator  
12 MHz and 32 kHz  
Oscillator  
PLL and Clock  
Generator  
Power-on-Reset  
256K Bytes  
Flash  
Program  
Memory  
8K Bytes  
Flash  
Data  
10K Bytes  
Static  
RAM  
Serial  
Debug  
Interface  
CR16C  
CPU Core  
CAN  
CPU Core Bus  
Bus  
Interface  
Unit  
Peripheral  
Bus  
Controller  
Interrupt  
Control  
Unit  
Power  
Manage-  
ment  
Timing and  
Watchdog  
Unit  
DMA  
Controller  
CVSD/PCM  
Peripheral Bus  
Audio  
Interface  
Microwire/  
SPI  
ACCESS  
.bus  
Versatile  
Timer Unit  
Muti-Func-  
tion Timer  
Multi-Input  
Wake-Up  
GPIO  
UART  
DS138  
TRI-STATE is a registered trademark of National Semiconductor Corporation.  
©2005 National Semiconductor Corporation  
www.national.com  

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