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CP3UB17G38X/NOPB PDF预览

CP3UB17G38X/NOPB

更新时间: 2024-01-27 03:52:20
品牌 Logo 应用领域
德州仪器 - TI 微控制器
页数 文件大小 规格书
200页 2991K
描述
IC,MICROCONTROLLER,16-BIT,CR16C CPU,QFP,100PIN,PLASTIC

CP3UB17G38X/NOPB 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:QFP, QFP100,.63SQ,20Reach Compliance Code:compliant
风险等级:5.84位大小:16
CPU系列:CR16CJESD-30 代码:S-PQFP-G100
JESD-609代码:e3湿度敏感等级:3
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP100,.63SQ,20
封装形状:SQUARE封装形式:FLATPACK
电源:2.5,2.5/3.3 V认证状态:Not Qualified
RAM(字节):10240ROM(单词):262144
ROM可编程性:FLASH速度:24 MHz
子类别:Microcontrollers最大压摆率:15 mA
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD

CP3UB17G38X/NOPB 数据手册

 浏览型号CP3UB17G38X/NOPB的Datasheet PDF文件第2页浏览型号CP3UB17G38X/NOPB的Datasheet PDF文件第3页浏览型号CP3UB17G38X/NOPB的Datasheet PDF文件第4页浏览型号CP3UB17G38X/NOPB的Datasheet PDF文件第5页浏览型号CP3UB17G38X/NOPB的Datasheet PDF文件第6页浏览型号CP3UB17G38X/NOPB的Datasheet PDF文件第7页 
PRELIMINARY  
Sept. 2003  
CP3UB17 Reprogrammable Connectivity Processor  
with USB Interface  
1.0 General Description  
The CP3UB17 connectivity processor combines a powerful The CP3UB17 is backed up by the software resources de-  
RISC core with on-chip SRAM and Flash memory for high signers need for rapid time-to-market, including an operat-  
computing bandwidth, hardware communications peripher- ing system, peripheral drivers, reference designs, and an  
als for high I/O bandwidth, and an external bus for system integrated development environment.  
expandability.  
National Semiconductor offers a complete and industry-  
On-chip communications peripherals include: USB control- proven application development environment for CP3UB17  
ler, ACCESS.bus, Microwire/Plus, SPI, UART, and Ad- applications, including the IAR Embedded Workbench,  
vanced Audio Interface (AAI). Additional on-chip peripherals iSYSTEM winIDEA and iC3000 Active Emulator, Develop-  
include DMA controller, PCM/CSVD conversion module, ment Board, and Application Software.  
Timing and Watchdog Unit, Versatile Timer Unit, Multi-  
Function Timer, and Multi-Input Wakeup.  
Block Diagram  
Clock Generator  
12 MHz and 32 kHz  
Oscillator  
PLL and Clock  
Generator  
Power-on-Reset  
256K Bytes  
Flash  
Program  
Memory  
8K Bytes  
Flash  
Data  
10K Bytes  
Static  
RAM  
Serial  
Debug  
Interface  
CR16C  
CPU Core  
CPU Core Bus  
Bus  
Interface  
Unit  
Peripheral  
Bus  
Controller  
Interrupt  
Control  
Unit  
Power  
Manage-  
ment  
Timing and  
Watchdog  
Unit  
DMA  
Controller  
CVSD/PCM  
Peripheral Bus  
Audio  
Interface  
Microwire/  
SPI  
ACCESS  
.bus  
Versatile  
Timer Unit  
Muti-Func-  
tion Timer  
Multi-Input  
Wake-Up  
USB  
GPIO  
UART  
DS131  
TRI-STATE is a registered trademark of National Semiconductor Corporation.  
©2003 National Semiconductor Corporation  
www.national.com  

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