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CLC5955MTD PDF预览

CLC5955MTD

更新时间: 2024-02-07 02:02:58
品牌 Logo 应用领域
德州仪器 - TI 信息通信管理光电二极管转换器
页数 文件大小 规格书
10页 221K
描述
IC,A/D CONVERTER,SINGLE,11-BIT,BICMOS,TSSOP,48PIN

CLC5955MTD 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:TSSOP, TSSOP48,.3,20Reach Compliance Code:compliant
Factory Lead Time:1 week风险等级:5.9
转换器类型:A/D CONVERTERJESD-30 代码:R-PDSO-G48
JESD-609代码:e0湿度敏感等级:2
位数:11功能数量:1
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出位码:2'S COMPLEMENT BINARY
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP48,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源:5 V
认证状态:Not Qualified子类别:Analog to Digital Converters
标称供电电压:5 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
Base Number Matches:1

CLC5955MTD 数据手册

 浏览型号CLC5955MTD的Datasheet PDF文件第4页浏览型号CLC5955MTD的Datasheet PDF文件第5页浏览型号CLC5955MTD的Datasheet PDF文件第6页浏览型号CLC5955MTD的Datasheet PDF文件第8页浏览型号CLC5955MTD的Datasheet PDF文件第9页浏览型号CLC5955MTD的Datasheet PDF文件第10页 
Physical Dimensions  
Symbol  
Min  
Max  
1.10  
0.15  
1.05  
0.27  
0.23  
0.20  
0.16  
12.60  
Notes  
A
A1  
A2  
b
0.05  
0.80  
0.17  
0.17  
0.09  
0.09  
12.40  
b1  
c
c1  
D
2
2
E
8.1 BSC  
E1  
6.00  
0.50  
6.20  
e
L
0.50 BSC  
0.75  
L1  
R1  
1.00 REF  
0.127  
Notes:  
1. All dimensions are in millimeters.  
2. Dimensions D and E1 do not include mold protrusion.  
Allowable protrusion is 0.20mm per side.  
CLC5955 Pin Denitions  
A , A  
(Pins 13, 14) Differential input with a common mode  
IN IN  
GND  
GND  
1
2
3
4
5
6
7
8
9
48 GND  
47 GND  
46 +DVCC  
45 D10 (MSB)  
44 D9  
voltage of +2.4V. The ADC full scale input is 1.024V  
on each of the complimentary input signals.  
pp  
GND  
GND  
ENCODE,  
ENCODE  
(Pins 9, 10) Differential clock where ENCODE initiates a  
new data conversion cycle on each rising edge. Logic for  
these inputs are 50% duty cycle universal differential signal  
+AVCC  
+AVCC  
+AVCC  
GND  
43 D8  
(>200mV). The clock input is internally biased to V /2 with  
42 D7  
CC  
CLC5955  
a termination impedance of 2.5k.  
41 D6  
ENCODE  
40 D5  
D0-D10  
(Pins 31-34, 39-45) Digital data outputs are CMOS and  
TTL compatible. D0 is the LSB and D10 is the MSB. MSB  
is inverted. Output coding is two’s complement.  
Current limited to source/sink 2.5mA typical.  
ENCODE 10  
GND 11  
GND 12  
AIN 13  
39 D4  
38 +DVCC  
37 +DVCC  
36 GND  
35 GND  
34 D3  
AIN 14  
DAV  
(Pin 27) Data Valid Clock. Data is valid on rising edge.  
Current limited to source/sink 5mA typical.  
GND 15  
+AVCC 16  
+AVCC 17  
+AVCC 18  
GND 19  
GND 20  
VCM 21  
33 D2  
32 D1  
OUTLEV  
(Pin 28) Output Logic 3.3V or 2.5V option.  
Open = 3.3V, GND = 2.5V.  
31 D0 (LSB)  
30 OGND  
29 NC  
V
(Pin 21) Internal common mode voltage reference. Nominally  
CM  
+2.4V. Can be used for the input common mode voltage.  
This voltage is derived from an internal bandgap reference.  
VCM should be buffered when driving any external load.  
Failure to buffer this signal can cause errors in the internal  
bias currents.  
28 OUTLEV  
27 DAV  
26 GND  
25 GND  
+AVCC 22  
GND 23  
GND 24  
GND  
(Pins 1-4, 8, 11, 12, 15, 19, 20, 23-26, 35, 36, 47, 48)  
circuit ground.  
+AV  
+DV  
NC  
(Pins 5-7, 16-18, 22,) +5V power supply for the analog  
section. Bypass to ground with a 0.1µF capacitor.  
CC  
(Pins 37, 38, 46) +5V power supply for the digital section.  
Bypass to ground with a 0.1µF capacitor.  
CC  
(Pin 29) No connect. May be left open or grounded.  
OGND  
(Pin 30) Option ground. May be tied to GND or left floating.  
CLC5955  
7
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