October 1999
N
CLC5957
12-bit, 70MSPS Broadband Monolithic A/D Converter
General Description
Features
The CLC5957 is a monolithic 12-bit, 70MSPS analog-to-digital
converter. The device has been optimized for use in IF-sampled
digital receivers and other applications where high resolution,
high sampling rate, wide dynamic range, low power dissipation,
and compact size are required. The CLC5957 features differential
analog inputs, low jitter differential universal clock inputs, a low
distortion track-and-hold with 0-300MHz input bandwidth, a band-
gap voltage reference, data valid clock output, TTL compatible
CMOS (3.3V or 2.5V) programmable output logic, and a propri-
etary 12-bit multi-stage quantizer. The CLC5957 is fabricated on
the ABIC-V 0.8 micron BiCMOS process.
• 70MSPS
• Wide dynamic range
SFDR: 74dBc
SFDR w/dither: 85dBFS
SNR: 67dB
• IF sampling capability
• Input bandwidth = 0-300MHz
• Low power dissipation: 640mW
• Very small package: 48-pin TSSOP
• Single +5V supply
• Data valid clock output
• Programmable output levels:
3.3V or 2.5V
The CLC5957 features a 74dBc spurious free dynamic range
(SFDR) and a 67dB signal to noise ratio (SNR). The wideband
track-and-hold allows sampling of IF signals to greater than
250MHz. The part produces two-tone, dithered, SFDR of 83dBFS
at 75MHz input frequency. The differential analog input provides
excellent common mode rejection, while the differential universal
clock inputs minimize jitter. The 48-pin TSSOP package provides
an extremely small footprint for applications where space is a
critical consideration. The CLC5957 operates from a single +5V
power supply. Operation over the industrial temperature range of
-40°C to +85°C is guaranteed. National Semiconductor tests
each part to verify compliance with the guaranteed specifications.
Applications
• Cellular base-stations
• Digital communications
• Infrared/CCD imaging
• IF sampling
• Electro-optics
• Instrumentation
• Medical imaging
• High definition video
ME79TG
CL5C9559657
Actual Size
MIMTTDD
N
ADC Block Diagram
First IF Receiver
DAV
Clock
In
CLC5902
DVGA
(∆G = 42dB)
IF
CLC5957
12-bit
70MSPS
ADC
Saw
Dig.
Tuner/
Filter
AGC
IF
Input
12
20
~
~
3-bit
Q
3-bit
Q
3-bit
Q
3-bit
Q
BPF
(150MHz
typ.)
A
In
T/H
DAV
Noise
BPF
3-bit (Gain Control)
3
3
3
3
12
ADC
Out
Decimation/filter = 190/0.8
Output BW = 50M/190 X 0.8 = 210KHz
Bit Align/Error Correct
Receiver SINAD vs. Input Amplitude
Single Tone Output Spectrum w/Dither
90
80
70
60
50
40
30
20
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
F
= 25.3MHZ
in
F
= 66MHz
sample
-100
0
0
4
8
12
16
20
24
28
32
-125
-100
-75
-50
-25
0
Frequency (MHz)
Input (dBFS)
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com