Datasheet > CLC5957

CLC5957

更新时间： 2024-02-25 21:50:37

品牌	Logo	应用领域
美国国家半导体 - NSC		转换器
页数	文件大小	规格书
12页	631K
描述
12-bit, 70MSPS Broadband Monolithic A/D Converter

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技术参数
数据手册

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CLC5957 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.83	转换器类型：	ADC, PROPRIETARY METHOD
输出位码：	OFFSET BINARY	Base Number Matches：	1

CLC5957 数据手册

CLC5957 Applications

Analog Inputs and Bias

ENCODE Clock Inputs

Figure 1 depicts the analog input and bias scheme. Each

of the differential analog inputs are internally biased to a

nominal voltage of 2.40 volts DC through a 500Ω resistor

to a low impedance buffer. This enables a simple

interface to a broadband RF transformer with a center-

tapped output winding that is decoupled to the analog

ground. If the application requires the inputs to be DC

The CLC5957’s differential input clock scheme is

compatible with all commonly used clock sources.

Although small differential and single-ended signals are

adequate, for best aperture jitter performance a low noise

differential clock with a high slew rate is preferred. As

depicted in Figure 3, both ENCODE clock inputs are

internally biased to V /2 though a pair of 5KΩ resistors.

coupled, the V

output can be used to establish the

The clock input buffer operates with any common-mode

voltage between the supply and ground.

proper common -mode input voltage for the ADC. The

voltage reference is generated from an internal

V_CCA

bandgap source that is very accurate and stable.

5kΩ

ADC

Bias Mirror

A_in

To T/H

and ADC

ENC

500Ω

2KΩ

1.23V

Bandgap

Reference

2.4V

V_cm

–

5kΩ

BJT Current Mirror

GNDA

Figure 1: CLC5957 Bias Scheme

output may also be used to power down the

Figure 3: CLC5957 ENCODE Clock Inputs

The V

The internal bias resistors simplify the clock interface to

another center-tapped transformer as depicted in Figure

4. A low phase noise, RF synthesizer of moderate ampli-

ADC. When the V pin is pulled above 3.5V, the internal

bias mirror is disabled and the total current is reduced to

less than 10mA. Figure 2 depicts how this function can

be used. The diode is necessary to prevent the logic gate

from altering the ADC bias value.

tude (1 - 4V ) can drive the ADC through this interface.

ENC

CLC5957

5V CMOS

"1" = on

"0" = off

V_ref

Figure 2: Power Shutdown Scheme

Figure 4:Transfer Coupled Clock Scheme

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