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CDC339DBR PDF预览

CDC339DBR

更新时间: 2024-11-13 12:34:07
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
13页 281K
描述
CLOCK DRIVER WITH 3-STATE OUTPUTS

CDC339DBR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:GREEN, PLASTIC, SSOP-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:7.87Is Samacsys:N
系列:CDC输入调节:STANDARD
JESD-30 代码:R-PDSO-G20长度:7.2 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.048 A
功能数量:1反相输出次数:
端子数量:20实输出次数:8
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):9 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.9 ns座面最大高度:2 mm
子类别:Clock Drivers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm
最小 fmax:80 MHzBase Number Matches:1

CDC339DBR 数据手册

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ꢀ ꢁꢀ ꢂꢂ ꢃ  
ꢀꢄ ꢅ ꢀꢆ ꢁ ꢇꢈ ꢉ ꢊꢇ  
ꢋ ꢈꢌ ꢍ ꢂ ꢎꢏꢌꢐꢌ ꢊ ꢅ ꢑꢌ ꢒꢑ ꢌꢏ  
SCAS331 − DECEMBER 1992 − REVISED MARCH 1994  
DB OR DW PACKAGE  
(TOP VIEW)  
D Low Output Skew, Low Pulse Skew for  
Clock-Distribution and Clock-Generation  
Applications  
Y3  
GND  
Y4  
Y2  
GND  
Y1  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
D TTL-Compatible Inputs and Outputs  
D Distributes One Clock Input to Eight  
Outputs  
V
V
CC  
CC  
− Four Same-Frequency Outputs  
− Four Half-Frequency Outputs  
OE  
CLK  
CLR  
GND  
D Distributed V  
and Ground Pins Reduce  
V
V
CC  
CC  
CC  
Switching Noise  
Q4  
GND  
Q3  
13 Q1  
12 GND  
D High-Drive Outputs (48-mA I  
,
OH  
11  
Q2  
48-mA I  
)
OL  
D State-of-the-Art EPIC-ΙΙBBiCMOS Design  
Significantly Reduces Power Dissipation  
D Package Options Include Plastic  
Small-Outline (DW) and Shrink  
Small-Outline (DB) Packages  
description  
The CDC339 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring  
synchronized output signals at both the primary clock frequency and one-half the primary clock frequency. The  
four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch  
at one-half the frequency of CLK.  
When the output-enable (OE) input is low and the clear (CLR) input is high, the Y outputs follow CLK and the  
Q outputs toggle on low-to-high transitions of CLK. Taking CLR low asynchronously resets the Q outputs to the  
low level. When OE is high, the outputs are in the high-impedance state.  
The CDC339 is characterized for operation from 40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
OE  
H
L
CLR  
X
CLK  
X
Y1−Y4 Q1Q4  
Z
L
Z
L
L
L
L
L
L
H
H
L
L
H
L
Q
0
0
L
H
H
Q
The level of the Q outputs before the  
indicated steady-state input conditions were  
established.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
ꢒꢇ ꢅ ꢁꢑ ꢀ ꢌꢈ ꢅ ꢓ ꢁ ꢐꢌꢐ ꢔꢕ ꢖ ꢗꢘ ꢙ ꢚꢛ ꢔꢗꢕ ꢔꢜ ꢝꢞ ꢘ ꢘ ꢟꢕꢛ ꢚꢜ ꢗꢖ ꢠꢞꢡ ꢢꢔꢝ ꢚꢛ ꢔꢗꢕ ꢣꢚ ꢛꢟ ꢤ  
ꢒꢘ ꢗ ꢣꢞꢝ ꢛ ꢜ ꢝ ꢗꢕ ꢖꢗ ꢘ ꢙ ꢛ ꢗ ꢜ ꢠꢟ ꢝ ꢔꢖ ꢔꢝꢚ ꢛꢔ ꢗꢕꢜ ꢠꢟ ꢘ ꢛꢥ ꢟ ꢛꢟ ꢘ ꢙꢜ ꢗꢖ ꢌꢟꢦ ꢚꢜ ꢈꢕꢜ ꢛꢘ ꢞꢙ ꢟꢕꢛ ꢜ  
ꢜ ꢛ ꢚ ꢕꢣ ꢚ ꢘꢣ ꢧ ꢚ ꢘꢘ ꢚ ꢕ ꢛꢨꢤ ꢒꢘ ꢗ ꢣꢞꢝ ꢛꢔꢗꢕ ꢠꢘ ꢗꢝ ꢟꢜ ꢜꢔ ꢕꢩ ꢣꢗꢟ ꢜ ꢕꢗꢛ ꢕꢟ ꢝꢟ ꢜꢜ ꢚꢘ ꢔꢢ ꢨ ꢔꢕꢝ ꢢꢞꢣ ꢟ  
ꢛ ꢟ ꢜ ꢛꢔ ꢕꢩ ꢗꢖ ꢚ ꢢꢢ ꢠꢚ ꢘ ꢚ ꢙ ꢟ ꢛ ꢟ ꢘ ꢜ ꢤ  
Copyright 1994, Texas Instruments Incorporated  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

CDC339DBR 替代型号

型号 品牌 替代类型 描述 数据表
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