Datasheet > CD74HCT563

CD74HCT563

更新时间： 2024-01-26 15:33:18

品牌	Logo	应用领域
德州仪器 - TI		锁存器
页数	文件大小	规格书
9页	53K
描述
High Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

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CD74HCT563 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	SOP, SOP20,.4	Reach Compliance Code：	unknown
风险等级：	5.92	JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e0	负载电容（CL）：	50 pF
逻辑集成电路类型：	D LATCH	最大I（ol）：	0.006 A
位数：	8	功能数量：	1
端子数量：	20	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP20,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	电源：	5 V
Prop。Delay @ Nom-Sup：	38 ns	子类别：	FF/Latches
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
Base Number Matches：	1

CD74HCT563 数据手册

CD74HC533, CD74HCT533,

CD74HC563, CD74HCT563

Data sheet acquired from Harris Semiconductor

SCHS187

High Speed CMOS Logic Octal Inverting

Transparent Latch, Three-State Outputs

January 1998

Features

Description

• Common Latch-Enable Control

• Common Three-State Output Enable Control

• Buffered Inputs

The Harris CD74HC533, CD74HCT533, CD74HC563, and

CD74HCT563 are high speed Octal Transparent Latches

manufactured with silicon gate CMOS technology. They pos-

sess the low power consumption of standard CMOS inte-

grated circuits, as well as the ability to drive 15 LSTTL

devices.

[ /Title

(CD74H

C533,

CD74H

CT533,

CD74H

C563,

CD74H

CT563)

/Subject

(High

• Three-State Outputs

• Bus Line Driving Capacity

The outputs are transparent to the inputs when the latch

enable (LE) is high. When the latch enable (LE) goes low the

data is latched. The output enable (OE) controls the three-

state outputs. When the output enable (OE) is high the

outputs are in the high impedance state. The latch operation

• Typical Propagation Delay = 13ns at V

= 5V,

C = 15pF, T = 25 C (Data to Output)

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

is independent to the state of the output enable.

The CD74HC533 and CD74HCT533 are identical in function

to the CD74HC563 and CD74HCT563 but have different

pinouts. The CD74HC533 and CD74HCT533 are similar to

the CD74HC373 and CD74HCT373; the latter are non-

inverting types.

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

Speed

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

Ordering Information

• HC Types

- 2V to 6V Operation

TEMP. RANGE

PKG.

NO.

PART NUMBER

CD74HC533E

CD74HCT533E

CD74HC563E

CD74HCT563E

CD74HCT563M

NOTES:

( C)

PACKAGE

20 Ld PDIP

20 Ld SOIC

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

at V

= 5V

-55 to 125

F20.3

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

E20.3

M20.3

V = 0.8V (Max), V = 2V (Min)

IL IH

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

2. Wafer and die for this part number are available which meets all

electrical specifications. Please contact your local sales office or

Harris customer service for ordering information.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 1599.1

12 3 4 5 6 7...9

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与CD74HCT563相关器件

型号	品牌	获取价格	描述	数据表
CD74HCT563E	TI	获取价格	High Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs
CD74HCT563EE4	TI	获取价格	High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs
CD74HCT563EN	ETC	获取价格	Logic IC
CD74HCT563EX	RENESAS	获取价格	HCT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDIP20
CD74HCT563F	ETC	获取价格	Logic IC
CD74HCT563H	ETC	获取价格	8-Bit D-Type Latch
CD74HCT563M	TI	获取价格	High Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs
CD74HCT563M96	ETC	获取价格	8-Bit D-Type Latch
CD74HCT563ME4	TI	获取价格	High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs
CD74HCT563MG4	TI	获取价格	High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

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