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CD74HCT564M PDF预览

CD74HCT564M

更新时间： 2024-02-09 06:39:30
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
14页 286K
描述
High-Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggered

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CD74HCT564M 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：SOIC
包装说明：SOIC-20针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：0.77Is Samacsys：N
其他特性：BROADSIDE VERSION OF 534控制类型：ENABLE LOW
计数方向：UNIDIRECTIONAL系列：HCT
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：12.8 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大频率@ Nom-Sup：16000000 Hz
最大I（ol）：0.006 A湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP20,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TUBE
峰值回流温度（摄氏度）：260电源：5 V
最大电源电流（ICC）：0.08 mAProp。Delay @ Nom-Sup：44 ns
传播延迟（tpd）：53 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：7.5 mmBase Number Matches：1

CD74HCT564M 数据手册

 浏览型号CD74HCT564M的Datasheet PDF文件第2页浏览型号CD74HCT564M的Datasheet PDF文件第3页浏览型号CD74HCT564M的Datasheet PDF文件第4页浏览型号CD74HCT564M的Datasheet PDF文件第5页浏览型号CD74HCT564M的Datasheet PDF文件第6页浏览型号CD74HCT564M的Datasheet PDF文件第7页 
CD54/74HC534, CD54/74HCT534,  
CD54/74HC564, CD54/74HCT564  
Data sheet acquired from Harris Semiconductor  
SCHS188C  
High-Speed CMOS Logic Octal D-Type Flip-Flop,  
Three-State Inverting Positive-Edge Triggered  
January 1998 - Revised April 2004  
Features  
Description  
• Buffered Inputs  
The ’HC534, ’HCT534, ’HC564, and ’HCT564 are high speed  
Octal D-Type Flip-Flops manufactured with silicon gate CMOS  
• Common Three-State Output-Enable Control  
• Three-State Outputs  
[ /Title  
(CD74  
HC534  
,
technology. They possess the low power consumption of stan-  
dard CMOS integrated circuits, as well as the ability to drive  
15 LSTTL loads. Due to the large output drive capability and  
the three-state feature, these devices are ideally suited for  
interfacing with bus lines in a bus organized system. The two  
types are functionally identical and differ only in their pinout  
arrangements.  
• Bus Line Driving Capability  
• Typical Propagation Delay = 13ns at V  
CC  
= 5V,  
CD74  
HCT53  
4,  
CD74  
HC564  
,
o
C = 15pF, T = 25 C (Clock to Output)  
L
A
• Fanout (Over Temperature Range)  
The ’HC534, ’HCT534, ’HC564, and ’HCT564 are positive  
edge triggered flip-flops. Data at the D inputs, meeting the  
setup and hold time requirements, are inverted and trans-  
ferred to the Q outputs on the positive going transition of the  
CLOCK input. When a high logic level is applied to the OUT-  
PUT ENABLE input, all outputs go to a high impedance state,  
regardless of what signals are present at the other inputs and  
the state of the storage elements.  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
CD74  
HCT56  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
The HCT logic family is speed, function, and pin compatible  
with the standard LS logic family.  
• HC Types  
- 2V to 6V Operation  
Ordering Information  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
TEMP. RANGE  
o
CC  
PART NUMBER  
CD54HC534F3A  
CD54HC564F3A  
CD54HCT534F3A  
CD54HCT564F3A  
CD74HC534E  
( C)  
PACKAGE  
20 Ld CERDIP  
20 Ld CERDIP  
20 Ld CERDIP  
20 Ld CERDIP  
20 Ld PDIP  
• HCT Types  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
CD74HC564E  
20 Ld PDIP  
CD74HC564M  
20 Ld SOIC  
20 Ld SOIC  
20 Ld PDIP  
CD74HC564M96  
CD74HCT534E  
CD74HCT564E  
CD74HCT564M  
20 Ld PDIP  
20 Ld SOIC  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2004, Texas Instruments Incorporated  
1
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中文翻译

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CD74HCT564M 替代型号

型号 品牌 替代类型 描述 数据表
CD74HCT564E TI

完全替代

 High Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggere
CD74HCT563M TI

类似代替

 High Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs
CD74HCT534E TI

类似代替

 High Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggere

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CD74HCT564ME4 TI

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 		High-Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggere
CD74HCT564MG4 TI

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 		High-Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggere
CD74HCT573 HARRIS

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 		High Speed CMOS Logic Octal Transparent Latch, Three-State Output
CD74HCT573 TI

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 		High Speed CMOS Logic Octal Transparent Latch, Three-State Output
CD74HCT573DBR TI

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 		OCTAL TRANSPARENT D-TYPE LATCHES WITH 3 STATE OUTPUTS
CD74HCT573DBRE4 TI

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 		High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs 20-SSOP -55 to 125
CD74HCT573DBRG4 TI

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 		HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, SSOP-20
CD74HCT573E TI

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 		High Speed CMOS Logic Octal Transparent Latch, Three-State Output
CD74HCT573E HARRIS

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 		High Speed CMOS Logic Octal Transparent Latch, Three-State Output

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