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CD74HCT563ME4

更新时间： 2024-01-15 00:57:53
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
14页 282K
描述
High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

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CD74HCT563ME4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOIC-20
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.19
Is Samacsys：N其他特性：BROADSIDE VERSION OF 533
系列：HCTJESD-30 代码：R-PDSO-G20
JESD-609代码：e4长度：12.8 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.006 A湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP20,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：5 VProp。Delay @ Nom-Sup：45 ns
传播延迟（tpd）：53 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.5 mm
Base Number Matches：1

CD74HCT563ME4 数据手册

 浏览型号CD74HCT563ME4的Datasheet PDF文件第2页浏览型号CD74HCT563ME4的Datasheet PDF文件第3页浏览型号CD74HCT563ME4的Datasheet PDF文件第4页浏览型号CD74HCT563ME4的Datasheet PDF文件第5页浏览型号CD74HCT563ME4的Datasheet PDF文件第6页浏览型号CD74HCT563ME4的Datasheet PDF文件第7页 
CD54/74HC533, CD54/74HCT533,  
CD54/74HC563, CD74HCT563  
Data sheet acquired from Harris Semiconductor  
SCHS187C  
High-Speed CMOS Logic Octal Inverting  
Transparent Latch, Three-State Outputs  
January 1998 - Revised July 2003  
Features  
Description  
• Common Latch-Enable Control  
• Common Three-State Output Enable Control  
• Buffered Inputs  
The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are  
high-speed Octal Transparent Latches manufactured with  
silicon gate CMOS technology. They possess the low power  
consumption of standard CMOS integrated circuits, as well as  
the ability to drive 15 LSTTL devices.  
[ /Title  
(CD74H  
C533,  
• Three-State Outputs  
CD74H  
CT533,  
CD74H  
C563,  
CD74H  
CT563)  
/Subject  
(High  
The outputs are transparent to the inputs when the latch  
enable (LE) is high. When the latch enable (LE) goes low the  
data is latched. The output enable (OE) controls the  
three-state outputs. When the output enable (OE) is high the  
outputs are in the high impedance state. The latch operation  
is independent of the state of the output enable.  
• Bus Line Driving Capacity  
• Typical Propagation Delay = 13ns at V  
CC  
= 5V,  
o
C = 15pF, T = 25 C (Data to Output)  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
The ’HC533 and ’HCT533 are identical in function to the  
’HC563 and CD74HCT563 but have different pinouts. The  
’HC533 and ’HCT533 are similar to the ’HC373 and ’HCT373;  
the latter are non-inverting types.  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Speed  
Ordering Information  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
TEMP. RANGE  
o
• HC Types  
- 2V to 6V Operation  
PART NUMBER  
CD54HC533F3A  
CD54HC563F3A  
CD54HCT533F3A  
CD74HC533E  
( C)  
PACKAGE  
20 Ld CERDIP  
20 Ld CERDIP  
20 Ld CERDIP  
20 Ld PDIP  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
CD74HC563E  
20 Ld PDIP  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
CD74HC563M  
20 Ld SOIC  
20 Ld PDIP  
l
CD74HCT533E  
CD74HCT563E  
CD74HCT563M  
20 Ld PDIP  
20 Ld SOIC  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
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CD74HCT563ME4 替代型号

型号 品牌 替代类型 描述 数据表
CD74HCT563M TI

类似代替

 High Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs
74HCT563D,652 NXP

功能相似

 74HC(T)563 - Octal D-type transparent latch; 3-state; inverting SOP 20-Pin

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