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CD74HCT573

更新时间: 2024-11-27 05:18:23
品牌 Logo 应用领域
哈里斯 - HARRIS 锁存器
页数 文件大小 规格书
8页 51K
描述
High Speed CMOS Logic Octal Transparent Latch, Three-State Output

CD74HCT573 数据手册

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CD74HC373, CD74HCT373,  
CD54HC573, CD74HC573,  
S E M I C O N D U C T O R  
CD74HCT573  
High Speed CMOS Logic  
November 1997  
Octal Transparent Latch, Three-State Output  
Features  
Description  
• Common Latch Enable Control  
• Common Three-State Output Enable Control  
• Buffered Inputs  
The Harris CD74HC373, CD74HCT373, CD54HC573,  
CD74HC573, and CD74HCT573 are high speed Octal Trans-  
parent Latches manufactured with silicon gate CMOS technol-  
ogy. They possess the low power consumption of standard  
CMOS integrated circuits, as well as the ability to drive 15  
LSTTL devices. The CD74HCT373 and CD74HCT573 are  
functionally as well as pin compatible with the standard  
74LS373 and 74LS573.  
• Three-State Outputs  
• Bus Line Driving Capacity  
• Typical Propagation Delay = 12ns at V  
= 5V,  
C = 15pF, T = 25 C (Data to Output for HC373)  
CC  
o
The outputs are transparent to the inputs when the latch  
enable (LE) is high. When the latch enable (LE) goes low the  
data is latched. The output enable (OE) controls the three-  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
state outputs. When the output enable (OE) is high the  
outputs are in the high impedance state. The latch operation  
is independent to the state of the output enable. The 373 and  
573 are identical in function and differ only in their pinout  
arrangements.  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
Ordering Information  
TEMP. RANGE  
PKG.  
NO.  
• HC Types  
- 2V to 6V Operation  
o
PART NUMBER  
CD54HC573F  
CD74HC373E  
CD74HCT373E  
CD74HC573E  
CD74HCT573E  
CD74HC373M  
CD74HCT373M  
CD74HC573M  
CD74HCT573M  
NOTES:  
( C)  
PACKAGE  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
20 Ld CERDIP F20.3  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
20 Ld PDIP  
20 Ld PDIP  
20 Ld PDIP  
20 Ld PDIP  
20 Ld SOIC  
20 Ld SOIC  
20 Ld SOIC  
20 Ld SOIC  
F20.3  
E20.3  
E20.3  
E20.3  
M20.3  
M20.3  
M20.3  
M20.3  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
2. Wafer or die for this part number are available which meets all  
electrical specifications. Please contact your local sales office or  
Harris customer service for ordering information.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1679.1  
Copyright © Harris Corporation 1997  
1

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