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CD74HCT40103E PDF预览

CD74HCT40103E

更新时间： 2024-11-04 23:04:31
品牌 Logo 应用领域
德州仪器 - TI 计数器
页数 文件大小 规格书
9页 47K
描述
High Speed CMOS Logic 8-Stage Synchronous Down Counters

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CD74HCT40103E 技术参数

是否Rohs认证：符合生命周期：Active
零件包装代码：DIP包装说明：DIP-16
针数：16Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：6 weeks风险等级：1.45
Is Samacsys：N其他特性：TCO OUTPUT; RESET TO MAX COUNT
计数方向：DOWN系列：HCT
JESD-30 代码：R-PDIP-T16JESD-609代码：e4
长度：19.3 mm负载电容（CL）：50 pF
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：9000000 Hz最大I（ol）：0.004 A
工作模式：SYNCHRONOUS位数：8
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE包装方法：TUBE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
最大电源电流（ICC）：0.08 mAProp。Delay @ Nom-Sup：85 ns
传播延迟（tpd）：90 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Counters
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：6.35 mm最小 fmax：9 MHz
Base Number Matches：1

CD74HCT40103E 数据手册

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CD74HC40103,  
CD74HCT40103  
Data sheet acquired from Harris Semiconductor  
SCHS221  
High Speed CMOS Logic  
November 1997  
8-Stage Synchronous Down Counters  
Features  
Description  
• Synchronous or Asynchronous Preset  
• Cascadable in Synchronous or Ripple Mode  
The Harris CD74HC40103 and CD74HCT40103 are  
manufactured with high speed silicon gate technology and  
consist of an 8-stage synchronous down counter with a  
single output which is active when the internal count is zero.  
The 40103 contains a single 8-bit binary counter. Each has  
control inputs for enabling or disabling the clock, for clearing  
the counter to its maximum count, and for presetting the  
[ /Title  
(CD74H  
C40103,  
CD74H  
CT4010  
3)  
/Sub-  
ject  
(High  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C counter either synchronously or asynchronously. All control  
inputs and the TC output are active-low logic.  
• Balanced Propagation Delay and Transition Times  
In normal operation, the counter is decremented by one  
• Significant Power Reduction Compared to LSTTL  
count on each positive transition of the CLOCK (CP).  
Logic ICs  
Counting is inhibited when the TE input is high. The TC  
output goes low when the count reaches zero if the TE input  
is low, and remains low for one full clock period.  
• HC Types  
Speed  
CMOS  
Logic 8-  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
When the PE input is low, data at the P0-P7 inputs are  
clocked into the counter on the next positive clock transition  
regardless of the state of the TE input. When the PL input is  
low, data at the P0-P7 inputs are asynchronously forced into  
the counter regardless of the state of the PE, TE, or CLOCK  
inputs. Input P0-P7 represent a single 8-bit binary word for  
the 40103. When the MR input is low, the counter is  
IL  
IH  
CC  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL  
IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
asynchronously cleared to its maximum count of 255 ,  
l
OL OH  
10  
regardless of the state of any other input. The precedence  
relationship between control inputs is indicated in the truth  
table.  
Ordering Information  
PKG.  
NO.  
o
If all control inputs except TE are high at the time of zero  
count, the counters will jump to the maximum count, giving a  
counting sequence of 100 or 256 clock pulses long.  
PART NUMBER TEMP. RANGE ( C) PACKAGE  
CD74HC40103E  
CD74HCT40103E  
CD74HC40103M  
CD74HCT40103M  
NOTES:  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
16 Ld PDIP E16.3  
16 Ld PDIP E16.3  
16 Ld SOIC M16.15  
16 Ld SOIC M16.15  
The 40103 may be cascaded using the TE input and the TC  
output, in either a synchronous or ripple mode. These  
circuits possess the the low power consumption usually  
associated with CMOS circuitry, yet have speeds  
comparable to low power Schottky TTL circuits and can drive  
up to 10 LSTTL loads.  
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
2. Wafer or die for this part number is available which meets all elec-  
trical specifications. Please contact your local sales office or  
Harris customer service for ordering information.  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1596.1  
Copyright © Harris Corporation 1997  
1
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CD74HCT40103E 替代型号

型号 品牌 替代类型 描述 数据表
CD74HCT40103MT TI

完全替代

 High-Speed CMOS Logic 8-Stage Synchronous Down Counters
CD74HCT40103M TI

完全替代

 High Speed CMOS Logic 8-Stage Synchronous Down Counters
CD74HCT40103M96 TI

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 High-Speed CMOS Logic 8-Stage Synchronous Down Counters

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