CD74HCT259

更新时间： 2024-09-14 23:04:31

品牌	Logo	应用领域
德州仪器 - TI		锁存器
页数	文件大小	规格书
9页	65K
描述
High Speed CMOS Logic 8-Bit Addressable Latch

阅读下载

中文翻译

获取价格

数据手册
替代型号

如果您发现信息不准确，欢迎纠错

CD74HCT259 数据手册

CD74HC259,

CD74HCT259

Data sheet acquired from Harris Semiconductor

SCHS173

High Speed CMOS Logic

8-Bit Addressable Latch

November 1997

Features

Description

• Buffered Inputs and Outputs

• Four Operating Modes

• Typical Propagation Delay of 15ns at V

The Harris CD74HC259 and CD74HCT259 Addressable

Latch features the low-power consumption associated with

CMOS circuitry and has speeds comparable to low-power

Schottky.

[ /Title

(CD74

HC259

CD74

HCT25

= 5V,

C = 15pF, T = 25 C

This latches three active modes and one reset mode. When

both the Latch Enable (LE) and Master Reset (MR) inputs are

low (8-line Demultiplexer mode) the output of the addressed

latch follows the Data input and all other outputs are forced

low. When both MR and LE are high (Memory Mode), all

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55 C to 125 C outputs are isolated from the Data input, i.e., all latches hold

the last data presented before the LE transition from low to

high. A condition of LE low and MR high (Addressable Latch

mode) allows the addressed latch’s output to follow the data

input; all other latches are unaffected. The Reset mode (all

outputs low) results when LE is high and MR is low.

/Sub-

ject

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

(High

Speed

CMOS

Logic

8-Bit

Addres

sable

Latch)

• HC Types

- 2V to 6V Operation

Ordering Information

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

at V

= 5V

PKG.

PART NUMBER TEMP. RANGE ( C) PACKAGE

NO.

E16.3

• HCT Types

CD74HC259E

CD74HCT259E

CD74HC259M

CD74HCT259M

NOTES:

-55 to 125

16 Ld PDIP

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

16 Ld SOIC M16.15

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

2. Wafer or die for this part number is available which meets all elec-

trical specifications. Please contact your local sales office or

Harris customer service for ordering information.

Pinout

CD74HC259, CD74HCT259

(PDIP, SOIC)

TOP VIEW

16 V

15 MR

14 LE

13 D

12 Q7

11 Q6

10 Q5

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 1727.1

12 3 4 5 6 7...9

中文翻译

下载PDF

CD74HCT259 替代型号

型号	品牌	替代类型	描述	数据表
CD54HCT259	TI	功能相似	High-Speed CMOS Logic 8-Bit Addressable Latch

与CD74HCT259相关器件

型号	品牌	获取价格	描述	数据表
CD74HCT259E	TI	获取价格	High Speed CMOS Logic 8-Bit Addressable Latch
CD74HCT259EE4	TI	获取价格	High-Speed CMOS Logic 8-Bit Addressable Latch
CD74HCT259EN	ETC	获取价格	Logic IC
CD74HCT259EX	RENESAS	获取价格	IC,LATCH,SINGLE,8-BIT,HCT-CMOS,DIP,16PIN,PLASTIC
CD74HCT259F	ETC	获取价格	Logic IC
CD74HCT259H	ETC	获取价格	Addressable D-Type Latch
CD74HCT259M	TI	获取价格	High Speed CMOS Logic 8-Bit Addressable Latch
CD74HCT259M96	TI	获取价格	High-Speed CMOS Logic 8-Bit Addressable Latch
CD74HCT259M96E4	TI	获取价格	High-Speed CMOS Logic 8-Bit Addressable Latch
CD74HCT259M96G4	TI	获取价格	High-Speed CMOS Logic 8-Bit Addressable Latch

与CD74HCT259相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

6
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

6
SL74HC10N：高性能三输入与非门解析
2024-09-03

84
AIC1781A 电池充电控制器深度解析
2024-09-03

78

产品中心

服务支持

精选活动

关于我们

帮助中心

CD74HCT259

CD74HCT259 数据手册

CD74HCT259 替代型号

与CD74HCT259相关器件

与CD74HCT259相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CD74HCT259

CD74HCT259 数据手册

CD74HCT259 替代型号

与CD74HCT259相关器件

与CD74HCT259相关文章

您还可以找

您在本页遇到什么问题？