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CD74HCT273EE4 PDF预览

CD74HCT273EE4

更新时间: 2024-11-10 11:06:59
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路触发器锁存器
页数 文件大小 规格书
13页 294K
描述
具有复位功能的高速 CMOS 逻辑八路 D 型触发器 | N | 20 | -55 to 125

CD74HCT273EE4 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:DIP
包装说明:DIP-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:5.3
Is Samacsys:N系列:HCT
JESD-30 代码:R-PDIP-T20JESD-609代码:e4
长度:24.33 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:16000000 Hz
最大I(ol):0.004 A位数:8
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):0.08 mA
Prop。Delay @ Nom-Sup:45 ns传播延迟(tpd):45 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:6.35 mm
最小 fmax:16 MHzBase Number Matches:1

CD74HCT273EE4 数据手册

 浏览型号CD74HCT273EE4的Datasheet PDF文件第2页浏览型号CD74HCT273EE4的Datasheet PDF文件第3页浏览型号CD74HCT273EE4的Datasheet PDF文件第4页浏览型号CD74HCT273EE4的Datasheet PDF文件第5页浏览型号CD74HCT273EE4的Datasheet PDF文件第6页浏览型号CD74HCT273EE4的Datasheet PDF文件第7页 
CD54HC273, CD74HC273,  
CD54HCT273, CD74HCT273  
Data sheet acquired from Harris Semiconductor  
SCHS174B  
High-Speed CMOS Logic  
Octal D-Type Flip-Flop with Reset  
February 1998 - Revised May 2003  
Features  
Description  
• Common Clock and Asynchronous Master Reset  
• Positive Edge Triggering  
• Buffered Inputs  
The ’HC273 and ’HCT273 high speed octal D-Type flip-flops  
with a direct clear input are manufactured with silicon-gate  
CMOS technology. They possess the low power consumption  
of standard CMOS integrated circuits.  
[ /Title  
(CD74  
HC273  
,
CD74  
HCT27  
3)  
Information at the D inputis transferred to the Q outputs on  
the positive-going edge of the clock pulse. All eight flip-flops  
are controlled by a common clock (CP) and a common reset  
(MR). Resetting is accomplished by a low voltage level  
independent of the clock. All eight Q outputs are reset to a  
logic 0.  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
/Sub-  
ject  
Ordering Information  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
o
PART NUMBER  
CD54HC273F3A  
CD74HC273E  
TEMP. RANGE ( C)  
-55 to 125  
PACKAGE  
20 Ld CERDIP  
20 Ld PDIP  
(High  
Speed  
CMOS  
Logic  
Octal  
D-  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
CC  
-55 to 125  
IL  
IH  
at V  
= 5V  
CC  
CD74HC273M  
-55 to 125  
20 Ld SOIC  
20 Ld SOIC  
20 Ld CERDIP  
20 Ld PDIP  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
CD74HC273M96  
CD54HCT273F3A  
CD74HCT273E  
CD74HCT273M  
CD74HCT273M96  
-55 to 125  
-55 to 125  
Type  
Flip-  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
-55 to 125  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
-55 to 125  
20 Ld SOIC  
20 Ld SOIC  
-55 to 125  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel.  
Pinout  
CD54HC273, CD54HCT273  
(CERDIP)  
CD74HC273, CD74HCT273  
(PDIP, SOIC)  
TOP VIEW  
1
2
3
4
5
6
7
8
9
V
MR  
Q0  
D0  
D1  
Q1  
Q2  
D2  
D3  
Q3  
20  
19  
CC  
Q7  
18 D7  
17 D6  
16 Q6  
15  
14  
Q5  
D5  
13 D4  
12  
Q4  
11 CP  
GND 10  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

CD74HCT273EE4 替代型号

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