CD74AC74,
CD74ACT74
Data sheet acquired from Harris Semiconductor
SCHS231
Dual D-Type Flip-Flop with Set and Reset
Positive-Edge-Triggered
September 1998
Features
Description
[ /Title
(CD74
AC74,
CD74
ACT74
)
/Sub-
ject
(Dual
D-
• Buffered Inputs
The Harris CD74AC74 and CD74ACT74 dual D-type, posi-
tive edge triggered flip-flops use the Harris ADVANCED
CMOS technology. These flip-flops have independent DATA,
SET, RESET, and CLOCK inputs and Q and Q outputs. The
logic level present at the data input is transferred to the out-
put during the positive going transition of the clock pulse.
SET and RESET are independent of the clock and are
accomplished by a low level at the appropriate input.
• Typical Propagation Delay (AC00)
o
- 4.9ns at V
= 5V, T = 25 C, C = 50pF
A L
CC
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Lachup-Resistant CMOS Process and Circuit
Design
Ordering Information
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
PART
NUMBER
TEMP.
RANGE ( C)
PKG.
NO.
o
PACKAGE
Type
Flip-
Flop
• Balanced Propagation Delays
CD74AC74E
CD74ACT74E
CD74AC74EX
CD74ACT74EX
CD74AC74M
CD74ACT74M
NOTES:
0 to 70, -40 to 85
-55 to 125
14 Ld PDIP
E14.3
E14.3
E14.3
E14.3
M14.15
M14.15
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
0 to 70, -40 to 85
-55 to 125
14 Ld PDIP
14 Ld PDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
with
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
Setand
Reset
Posi-
tive-
Edge-
Trig-
gered)
/Autho
r ()
/Key-
words
(Har-
ris
0 to 70, -40 to 85
-55 to 125
- Drives 50Ω Transmission Lines
0 to 70, -40 to 85
-55 to 125
0 to 70, -40 to 85
-55 to 125
0 to 70, -40 to 85
-55 to 125
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or Harris
customer service for ordering information.
Semi-
con-
Pinout
ductor,
Advan
ced
CD74AC74, CD74ACT74
(PDIP, SOIC)
TOP VIEW
CMOS
,Harris
Semi-
con-
ductor,
Advan
1R
1D
1
2
3
4
5
6
7
14 V
CC
13 2R
12 2D
11 2CP
10 2S
1CP
1S
1Q
1Q
9
8
2Q
2Q
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1998
File Number 1881.1
1