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CD74AC86EE4 PDF预览

CD74AC86EE4

更新时间: 2024-09-16 14:48:27
品牌 Logo 应用领域
德州仪器 - TI 输入元件光电二极管逻辑集成电路石英晶振触发器
页数 文件大小 规格书
13页 814K
描述
AC SERIES, QUAD 2-INPUT XOR GATE, PDIP14, ROHS COMPLIANT, PLASTIC, DIP-14

CD74AC86EE4 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:DIP
包装说明:ROHS COMPLIANT, PLASTIC, DIP-14针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.21Is Samacsys:N
系列:ACJESD-30 代码:R-PDIP-T14
JESD-609代码:e4长度:19.305 mm
负载电容(CL):50 pF逻辑集成电路类型:XOR GATE
最大I(ol):0.012 A功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3/5 V
Prop。Delay @ Nom-Sup:15.1 ns传播延迟(tpd):135 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:5.08 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.5 V
标称供电电压 (Vsup):3 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

CD74AC86EE4 数据手册

 浏览型号CD74AC86EE4的Datasheet PDF文件第2页浏览型号CD74AC86EE4的Datasheet PDF文件第3页浏览型号CD74AC86EE4的Datasheet PDF文件第4页浏览型号CD74AC86EE4的Datasheet PDF文件第5页浏览型号CD74AC86EE4的Datasheet PDF文件第6页浏览型号CD74AC86EE4的Datasheet PDF文件第7页 
CD74AC86  
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE  
SCHS324 – JANUARY 2003  
E OR M PACKAGE  
(TOP VIEW)  
AC Types Feature 1.5-V to 5.5-V Operation  
and Balanced Noise Immunity at 30% of the  
Supply  
1A  
1B  
1Y  
2A  
2B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
Speed of Bipolar F, AS, and S, With  
Significantly Reduced Power Consumption  
4B  
4A  
4Y  
Balanced Propagation Delays  
±24-mA Output Drive Current  
– Fanout to 15 F Devices  
10 3B  
2Y  
GND  
3A  
3Y  
9
8
SCR-Latchup-Resistant CMOS Process and  
Circuit Design  
Exceeds 2-kV ESD Protection Per  
MIL-STD-883, Method 3015  
description/ordering information  
The CD74AC86 is a quadruple 2-input exclusive-OR gate. This device performs the Boolean function  
Y = A B or Y = AB + AB in positive logic.  
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced  
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the  
output.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – E  
SOIC – M  
Tube  
Tube  
CD74AC86E  
CD74AC86M  
CD74AC86E  
–55°C to 125°C  
AC86M  
Tape and reel CD74AC86M96  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
L
L
L
L
H
H
L
H
L
H
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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